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VHDL - Symphony EDA read line error

 
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Old 10-28-2004, 03:37 PM   #1
Default Symphony EDA read line error


I use Symphony EDA VhdlE version 1.5 Build#8

I get a run-time error:

Error: CSSIM0034: tb.vhd: (line 104): Read from a bad LINE variable
Exception occurred. Cannot continue simulation

This is the vhdl code line that causes the truble (c is a character):
read(inp_line,c);

Just before crash I do
write(dbg_line, string'("dbg start "));
writeline(output, dbg_line);
writeline(output, inp_line);
write(dbg_line, string'("dbg end"));
writeline(output, dbg_line);
and this what I get
Symphony EDA (R) VHDL Compiler/Simulator Module VhdlE, Version 1.5, Build#8.
Copyright(C) Symphony EDA 1997-2000. All rights reserved.
Reading symphony.ini ...
Library 'ieee' ==> $SYMPHONY/Lib/Ieee/Ieee.sym (readonly)
Library 'synopsys' ==> $SYMPHONY/Lib/Synopsys/synopsys.sym (readonly)
Library 'work' ==> work.sym
Reading work.sym\tb\prim.var
Reading $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_textio\_body .var
Reading $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_1164\_body.v ar
Reading $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_unsigned\_bo dy.var
Reading $SYMPHONY\Lib\Ieee\Ieee.sym\std_logic_arith\_body. var
Reading work.sym\tb\_tb_arc.var
# of Signals = 538
# of Components = 0
# of Processes = 2
# of Drivers = 104
Design Load/Elaboration Elapsed Time: 00h:00m:00s:140ms
dbg start
0x10 4 0
dbg end
At tb.vhd: (line 104)
Instance = :tb(tb_arc):main_pci_master_command:
At tb.vhd: (line 14
Instance = :tb(tb_arc):


pini
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