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VHDL - Control Register implementation |
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I have a 8bit control register that in a PLD that resides at 0x330 on
an ISA bus. I want to be able to have some bits in the control register read-only, read/write, and write-only. I have something like this process (IOR) begin if (Falling_edge(IOR) and CRS = '0') then -- Place the Control register onto the databus but ensure the write-only -- Data is correct SD <= (reg and "11111110"); end if; end process; process (IOW) begin if (Falling_edge(IOW) and CRS = '0') then -- Read the data from the databus but don't write over the read-only bits reg(4) <= SD(4); reg(3) <= SD(3); reg(2) <= SD(2); reg(1) <= SD(1); reg(0) <= SD(0); end if; end process; However, doing it this way means that if I write data to the Data-bus I need to tri-state the databus somehow? How can I do this/ when and where??? Thanks gommo |
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