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VHDL - Procedures, variables and their scope. |
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#1 |
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Hi All,
I have a problem, as far as I know procedures can change signals/variables as long as the procedures are defined within the scope where the variables are defined. Yet when i try to simulate my vhdl code the ISE synthesizer gives me the following warning : WARNING:Xst:1960 - C:/projects/redemption/ax88796.vhd line 86: Potential simulation mismatch, variable <register_uit> declared in block <$PROCESS1> is assigned in block <WriteReg>. My code looks basicly like the code shown here. It seems like that the variables within the procedure do not change the variable outside the procedure, which is what i was hoping for. Is there any Macro command or something in vhdl, because that is what i am using the procedure for. With regards, Michel Bieleveld. entity ax88796 is ... end ax88796; architecture RTL of ax88796 is ... begin process (nRST,CLK) ... variable operand : std_logic_vector(15 downto 0); procedure ReadReg(Ax_reg : in std_logic_vector(7 downto 0))is begin operand := B"00001110" & Ax_reg; return_state := current_state; next_state := st_ExRead; end ReadReg; begin ... blahblah ReadReg(X"00"); ... end process; end rtl; Michel Bieleveld |
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#2 |
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Michel Bieleveld wrote:
> I have a problem, as far as I know procedures can change > signals/variables as long as the procedures are defined within the > scope where the variables are defined. Variables must be passed a parameters to a procedure. > It seems like that the > variables within the procedure do not change the variable outside the > procedure If you pass the process variable, the procedure can change its value. Variable scope is local to the procedure or process. Pass the variable or use a signal. -- Mike Treseler Mike Treseler |
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#3 |
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But I thought the difference between (pure) functions and procedures
is that procedures can have side effects. In this case changing a variable defined in the process from which I am calling the procedure. <Michel Bieleveld> Mike Treseler <> wrote in message news:<rOmdnbbU7q9TOeLcRVn->... > Michel Bieleveld wrote: > > > I have a problem, as far as I know procedures can change > > signals/variables as long as the procedures are defined within the > > scope where the variables are defined. > > Variables must be passed a parameters to a procedure. > > > It seems like that the > > variables within the procedure do not change the variable outside the > > procedure > > If you pass the process variable, the procedure can change > its value. Variable scope is local to the procedure or process. > Pass the variable or use a signal. > > -- Mike Treseler Michel Bieleveld |
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#4 |
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Michel Bieleveld wrote:
> But I thought the difference between (pure) functions and procedures > is that procedures can have side effects. True > In this case changing a > variable defined in the process from which I am calling the procedure. Yes, but only if the variable is passed from process scope to procedure scope. -- Mike Treseler Mike Treseler |
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#5 |
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"Mike Treseler" <> wrote in message news:caKdnYwPMemVtx3cRVn-... > Michel Bieleveld wrote: > > But I thought the difference between (pure) functions and procedures > > is that procedures can have side effects. > True > > > In this case changing a > > variable defined in the process from which I am calling the procedure. > > Yes, but only if the variable is passed from process scope > to procedure scope. > Hallo Mike, I don't think that's correct. Michel is right, a procedure declared within a process can directly access variables declared within the process, just as it can directly access signals declared within the architecture that contains that process. Regarding the original problem, Michel can you post your actual code? regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. Alan Fitch |
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#6 |
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Alan Fitch wrote:
> I don't think that's correct. Michel is right, a procedure > declared within a process can directly access variables declared within the > process, just as it can directly access signals declared within the > architecture that contains that process. Sorry about that. Yes you and Michel are right, and I did not read his example carefully. As long as the variable is declared before the procedure it is directly visible to that procedure. My comments applied to packaged procedures that can be called from any process. -- Mike Treseler Mike Treseler |
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