P2S

Hi,

I am trying to build a 19 bit parallel to serial conveter. I have one
state machine and a 5 bit counter. The problem is that its only
outputing the MSB bit from the 19 bit data. Please adivce soon ...The
code is as follows



---P2S-----
library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity PISO is

port (

parallel_in : in unsigned (18 downto 0); -- Parallel Register
,holds the 19- bits
latch : in std_logic; -- When low, loads the data into the
19-bit register
ds : in bit; -- Makes the parallel register shifts right or
left
ser_out : out bit; -- Serial data output pin
CLK : in std_logic; -- Clock for the serial shift
clk_out : out std_logic; -- Clock for the Digigtal to Analog
converter
synch : out std_logic; -- Synchronize the data frame
cpld_ready : out std_logic

);
end PISO;
Architecture PISO_ARCH of PISO IS

--------------------------------------------
Component counter_b
Port (
CLK_b : in std_logic;
P_b : in std_logic;
Load : in std_logic;
compare_signal : out std_logic
);
End Component;
-------------------------------------------------
signal State : unsigned(3 downto 0);
signal nextstate : unsigned(3 downto 0);
constant E0 : unsigned(3 downto 0):="0001";
constant E1 : unsigned(3 downto 0):="0010";
constant E2 : unsigned(3 downto 0):="0100";
constant E3 : unsigned(3 downto 0):="1000";
--Signal SM_DIR : std_logic;
-------------------------------------------------
Signal incrementB : std_logic;
Signal Load_counter : std_logic;
Signal compare : std_logic;
------------------------------------------------
Signal ser_buff: bit_vector ( 18 downto 0);

BEGIN
ser_out <= ser_buff(1;
clk_out <= latch and clk;
synch<= incrementB;
cpld_ready <=compare;
CB: counter_b port map (CLK, incrementB,Load_counter,compare);
--------------------------------------------------------------------------
Process(State,nextstate)
Begin
Case State is

When E0=>
incrementB<='0';
ser_buff<="0101010101010101010";
Load_counter<='1';
nextstate<=E1;


When E1=>
If (compare ='0') Then
incrementB<='1';
Load_counter<='0';
ser_buff(0) <= ds;
ser_buff(1) <= ser_buff(0);
ser_buff(2) <= ser_buff(1);
ser_buff(3) <= ser_buff(2);
ser_buff(4) <= ser_buff(3);
ser_buff(5) <= ser_buff(4);
ser_buff(6) <= ser_buff(5);
ser_buff(7) <= ser_buff(6);
ser_buff( <= ser_buff(7);
ser_buff(9) <= ser_buff(;
ser_buff(10) <= ser_buff(9);
ser_buff(11) <= ser_buff(10);
ser_buff(12) <= ser_buff(11);
ser_buff(13) <= ser_buff(12);
ser_buff(14) <= ser_buff(13);
ser_buff(15) <= ser_buff(14);
ser_buff(16) <= ser_buff(15);
ser_buff(17) <= ser_buff(16);
ser_buff(1 <= ser_buff(17);
nextstate<=E1;
Else

nextstate<=E0;
End If;



When others =>
nextstate <= E0;


End Case;

End Process;
--------------------------------------------------
Process (CLK)
Begin
If (CLK'event And CLK='1') Then
-- SM_DIR <= OE1;
State <= nextstate;

End If;
End Process;
End PISO_ARCH;


----Counter------

Library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
------------------------------------------------------------------
Entity counter_b is
Port (

CLK_b : in std_logic;
P_b : in std_logic;
Load : in std_logic;
compare_signal : out std_logic
);
End counter_b;
Architecture count_arch_b of counter_b is

Signal Q_b : unsigned (4 downto 0);
Signal data : unsigned (4 downto 0):="10011";
Begin

Process(CLK_b,Load)

Begin

If (Load='1')Then

Q_b <= ('0', '0', '0', '0', '0');
compare_signal <='0';


Else If (CLK_b='1' and CLK_b'event) then


If (P_b='1') Then
Q_b<=Q_b+1;
compare_signal <='0';

If (Q_b=data) Then
compare_signal <='1';
Q_b <= ('0', '0', '0', '0', '0');
End If;


End If;

--End If;
End if;
End If;
End process;
End count_arch_b ;

john

john wrote:
> Hi,
>
> I am trying to build a 19 bit parallel to serial conveter. I have one
> state machine and a 5 bit counter. The problem is that its only
> outputing the MSB bit from the 19 bit data. Please adivce soon ...The
> code is as follows
>
>
>
> ---P2S-----
> library IEEE;
> USE ieee.std_logic_1164.ALL;
> USE ieee.numeric_std.ALL;
> entity PISO is
>
> port (
>
> parallel_in : in unsigned (18 downto 0); -- Parallel Register
> ,holds the 19- bits
> latch : in std_logic; -- When low, loads the data into the
> 19-bit register
> ds : in bit; -- Makes the parallel register shifts right or
> left
> ser_out : out bit; -- Serial data output pin
> CLK : in std_logic; -- Clock for the serial shift
> clk_out : out std_logic; -- Clock for the Digigtal to Analog
> converter
> synch : out std_logic; -- Synchronize the data frame
> cpld_ready : out std_logic
>
> );
> end PISO;
> Architecture PISO_ARCH of PISO IS
>
> --------------------------------------------
> Component counter_b
> Port (
> CLK_b : in std_logic;
> P_b : in std_logic;
> Load : in std_logic;
> compare_signal : out std_logic
> );
> End Component;
> -------------------------------------------------
> signal State : unsigned(3 downto 0);
> signal nextstate : unsigned(3 downto 0);
> constant E0 : unsigned(3 downto 0):="0001";
> constant E1 : unsigned(3 downto 0):="0010";
> constant E2 : unsigned(3 downto 0):="0100";
> constant E3 : unsigned(3 downto 0):="1000";
> --Signal SM_DIR : std_logic;
> -------------------------------------------------
> Signal incrementB : std_logic;
> Signal Load_counter : std_logic;
> Signal compare : std_logic;
> ------------------------------------------------
> Signal ser_buff: bit_vector ( 18 downto 0);
>
> BEGIN
> ser_out <= ser_buff(1;
> clk_out <= latch and clk;
> synch<= incrementB;
> cpld_ready <=compare;
> CB: counter_b port map (CLK, incrementB,Load_counter,compare);
> --------------------------------------------------------------------------
> Process(State,nextstate)
> Begin
> Case State is
>
> When E0=>
> incrementB<='0';
> ser_buff<="0101010101010101010";
> Load_counter<='1';
> nextstate<=E1;
>
>
> When E1=>
> If (compare ='0') Then
> incrementB<='1';
> Load_counter<='0';
> ser_buff(0) <= ds;
> ser_buff(1) <= ser_buff(0);
> ser_buff(2) <= ser_buff(1);
> ser_buff(3) <= ser_buff(2);
> ser_buff(4) <= ser_buff(3);
> ser_buff(5) <= ser_buff(4);
> ser_buff(6) <= ser_buff(5);
> ser_buff(7) <= ser_buff(6);
> ser_buff( <= ser_buff(7);
> ser_buff(9) <= ser_buff(;
> ser_buff(10) <= ser_buff(9);
> ser_buff(11) <= ser_buff(10);
> ser_buff(12) <= ser_buff(11);
> ser_buff(13) <= ser_buff(12);
> ser_buff(14) <= ser_buff(13);
> ser_buff(15) <= ser_buff(14);
> ser_buff(16) <= ser_buff(15);
> ser_buff(17) <= ser_buff(16);
> ser_buff(1 <= ser_buff(17);
> nextstate<=E1;
> Else
>
> nextstate<=E0;
> End If;
>
>
>
> When others =>
> nextstate <= E0;
>
>
> End Case;
>
> End Process;
> --------------------------------------------------
> Process (CLK)
> Begin
> If (CLK'event And CLK='1') Then
> -- SM_DIR <= OE1;
> State <= nextstate;
>
> End If;
> End Process;
> End PISO_ARCH;
>
>
> ----Counter------
>
> Library IEEE;
> USE ieee.std_logic_1164.ALL;
> USE ieee.numeric_std.ALL;
> ------------------------------------------------------------------
> Entity counter_b is
> Port (
>
> CLK_b : in std_logic;
> P_b : in std_logic;
> Load : in std_logic;
> compare_signal : out std_logic
> );
> End counter_b;
> Architecture count_arch_b of counter_b is
>
> Signal Q_b : unsigned (4 downto 0);
> Signal data : unsigned (4 downto 0):="10011";
> Begin
>
> Process(CLK_b,Load)
>
> Begin
>
> If (Load='1')Then
>
> Q_b <= ('0', '0', '0', '0', '0');
> compare_signal <='0';
>
>
> Else If (CLK_b='1' and CLK_b'event) then
>
>
> If (P_b='1') Then
> Q_b<=Q_b+1;
> compare_signal <='0';
>
> If (Q_b=data) Then
> compare_signal <='1';
> Q_b <= ('0', '0', '0', '0', '0');
> End If;
>
>
> End If;
>
> --End If;
> End if;
> End If;
> End process;
> End count_arch_b ;

I think you need to use the counter as an index to ser_buff.
I don't no what happens when you assing somthing to ser_buff(0) and
ser_buff(1) and ser_buff ... at the sametime.

--
thomas

thomas

Hi thomas,
Thanks for ur reply! Would you please clear ur point more..
Thanks
Regards
john











thomas <> wrote in message news:<cliih6$1jbf$>...
> john wrote:
> > Hi,
> >
> > I am trying to build a 19 bit parallel to serial conveter. I have one
> > state machine and a 5 bit counter. The problem is that its only
> > outputing the MSB bit from the 19 bit data. Please adivce soon ...The
> > code is as follows
> >
> >
> >
> > ---P2S-----
> > library IEEE;
> > USE ieee.std_logic_1164.ALL;
> > USE ieee.numeric_std.ALL;
> > entity PISO is
> >
> > port (
> >
> > parallel_in : in unsigned (18 downto 0); -- Parallel Register
> > ,holds the 19- bits
> > latch : in std_logic; -- When low, loads the data into the
> > 19-bit register
> > ds : in bit; -- Makes the parallel register shifts right or
> > left
> > ser_out : out bit; -- Serial data output pin
> > CLK : in std_logic; -- Clock for the serial shift
> > clk_out : out std_logic; -- Clock for the Digigtal to Analog
> > converter
> > synch : out std_logic; -- Synchronize the data frame
> > cpld_ready : out std_logic
> >
> > );
> > end PISO;
> > Architecture PISO_ARCH of PISO IS
> >
> > --------------------------------------------
> > Component counter_b
> > Port (
> > CLK_b : in std_logic;
> > P_b : in std_logic;
> > Load : in std_logic;
> > compare_signal : out std_logic
> > );
> > End Component;
> > -------------------------------------------------
> > signal State : unsigned(3 downto 0);
> > signal nextstate : unsigned(3 downto 0);
> > constant E0 : unsigned(3 downto 0):="0001";
> > constant E1 : unsigned(3 downto 0):="0010";
> > constant E2 : unsigned(3 downto 0):="0100";
> > constant E3 : unsigned(3 downto 0):="1000";
> > --Signal SM_DIR : std_logic;
> > -------------------------------------------------
> > Signal incrementB : std_logic;
> > Signal Load_counter : std_logic;
> > Signal compare : std_logic;
> > ------------------------------------------------
> > Signal ser_buff: bit_vector ( 18 downto 0);
> >
> > BEGIN
> > ser_out <= ser_buff(1;
> > clk_out <= latch and clk;
> > synch<= incrementB;
> > cpld_ready <=compare;
> > CB: counter_b port map (CLK, incrementB,Load_counter,compare);
> > --------------------------------------------------------------------------
> > Process(State,nextstate)
> > Begin
> > Case State is
> >
> > When E0=>
> > incrementB<='0';
> > ser_buff<="0101010101010101010";
> > Load_counter<='1';
> > nextstate<=E1;
> >
> >
> > When E1=>
> > If (compare ='0') Then
> > incrementB<='1';
> > Load_counter<='0';
> > ser_buff(0) <= ds;
> > ser_buff(1) <= ser_buff(0);
> > ser_buff(2) <= ser_buff(1);
> > ser_buff(3) <= ser_buff(2);
> > ser_buff(4) <= ser_buff(3);
> > ser_buff(5) <= ser_buff(4);
> > ser_buff(6) <= ser_buff(5);
> > ser_buff(7) <= ser_buff(6);
> > ser_buff( <= ser_buff(7);
> > ser_buff(9) <= ser_buff(;
> > ser_buff(10) <= ser_buff(9);
> > ser_buff(11) <= ser_buff(10);
> > ser_buff(12) <= ser_buff(11);
> > ser_buff(13) <= ser_buff(12);
> > ser_buff(14) <= ser_buff(13);
> > ser_buff(15) <= ser_buff(14);
> > ser_buff(16) <= ser_buff(15);
> > ser_buff(17) <= ser_buff(16);
> > ser_buff(1 <= ser_buff(17);
> > nextstate<=E1;
> > Else
> >
> > nextstate<=E0;
> > End If;
> >
> >
> >
> > When others =>
> > nextstate <= E0;
> >
> >
> > End Case;
> >
> > End Process;
> > --------------------------------------------------
> > Process (CLK)
> > Begin
> > If (CLK'event And CLK='1') Then
> > -- SM_DIR <= OE1;
> > State <= nextstate;
> >
> > End If;
> > End Process;
> > End PISO_ARCH;
> >
> >
> > ----Counter------
> >
> > Library IEEE;
> > USE ieee.std_logic_1164.ALL;
> > USE ieee.numeric_std.ALL;
> > ------------------------------------------------------------------
> > Entity counter_b is
> > Port (
> >
> > CLK_b : in std_logic;
> > P_b : in std_logic;
> > Load : in std_logic;
> > compare_signal : out std_logic
> > );
> > End counter_b;
> > Architecture count_arch_b of counter_b is
> >
> > Signal Q_b : unsigned (4 downto 0);
> > Signal data : unsigned (4 downto 0):="10011";
> > Begin
> >
> > Process(CLK_b,Load)
> >
> > Begin
> >
> > If (Load='1')Then
> >
> > Q_b <= ('0', '0', '0', '0', '0');
> > compare_signal <='0';
> >
> >
> > Else If (CLK_b='1' and CLK_b'event) then
> >
> >
> > If (P_b='1') Then
> > Q_b<=Q_b+1;
> > compare_signal <='0';
> >
> > If (Q_b=data) Then
> > compare_signal <='1';
> > Q_b <= ('0', '0', '0', '0', '0');
> > End If;
> >
> >
> > End If;
> >
> > --End If;
> > End if;
> > End If;
> > End process;
> > End count_arch_b ;
>
> I think you need to use the counter as an index to ser_buff.
> I don't no what happens when you assing somthing to ser_buff(0) and
> ser_buff(1) and ser_buff ... at the sametime.

john

john wrote:
> Hi thomas,
> Thanks for ur reply! Would you please clear ur point more..
> Thanks
> Regards
> john

Hi John

im not very good at VHDL but her it is
if you want to clock the ser_buff data out you can use an index
then index is the value of Q_b (see below in counter)

the problem with you code,(I thing), is than you are making a glitch in
state E1 when assigning new values to ser_buff(x)

I made som changes to you code, i works for me know


library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity P2S is

port (

parallel_in : in bit_vector (18 downto 0); -- Parallel
Register,holds the 19- bits
latch : in std_logic; -- When low, loads the data into the
19-bit register
ds : in bit; -- Makes the parallel register shifts right
or left
ser_out : out bit; -- Serial data output pin
CLK : in std_logic; -- Clock for the serial shift
clk_out : out std_logic; -- Clock for the Digigtal to Analog
converter
synch : out std_logic; -- Synchronize the data frame
cpld_ready : out std_logic

);
end P2S;
architecture PISO_ARCH of P2S is

--------------------------------------------
component counter_b
port (
CLK_b : in std_logic;
P_b : in std_logic;
Load : in std_logic;
index : out unsigned(4 downto 0);
compare_signal : out std_logic
);
end component;
-------------------------------------------------
signal State : unsigned(3 downto 0);
signal nextstate : unsigned(3 downto 0);
constant E0 : unsigned(3 downto 0) := "0001";
constant E1 : unsigned(3 downto 0) := "0010";
constant E2 : unsigned(3 downto 0) := "0100";
constant E3 : unsigned(3 downto 0) := "1000";
--Signal SM_DIR : std_logic;
-------------------------------------------------
signal incrementB : std_logic;
signal Load_counter : std_logic;
signal compare : std_logic;
------------------------------------------------
signal ser_buff : bit_vector (18 downto 0);
signal index : unsigned(4 downto 0);
signal xser_out : bit; -- temp signal
begin

-- remove glitch
ser_out <= xser_out when compare = '0' and incrementB = '1' else '0';

clk_out <= latch and clk;
synch <= incrementB;
cpld_ready <= compare;

-- add index to counter
CB : counter_b port map (CLK, incrementB, Load_counter, index, compare);
--------------------------------------------------------------------------
process(State, nextstate)
begin
case State is

when E0 =>
incrementB <= '0';
--ser_buff <= "0101010101010101010";
ser_buff <= parallel_in; -- take input from toplevel
Load_counter <= '1';
nextstate <= E1;


when E1 =>
if (compare = '0') then
incrementB <= '1';
Load_counter <= '0';
xser_out <= ser_buff(to_integer(index));
nextstate <= E1;
else

nextstate <= E0;
end if;



when others =>
nextstate <= E0;


end case;

end process;
--------------------------------------------------
process (CLK)
begin
if (CLK'event and CLK = '1') then
-- SM_DIR <= OE1;
State <= nextstate;

end if;
end process;
end PISO_ARCH;


----Counter------

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------------
entity counter_b is
port (

CLK_b : in std_logic;
P_b : in std_logic;
Load : in std_logic;
index : out unsigned (4 downto 0);
compare_signal : out std_logic
);
end counter_b;
architecture count_arch_b of counter_b is
signal Q_b : unsigned (4 downto 0);
-- signal Q_b : natural range 0 to 13;
signal data : unsigned (4 downto 0) := "10011";
-- constant data : natural := 13;
begin

index <= Q_b; -- route Q_b to index

process(CLK_b, Load)

begin

if (Load = '1')then

Q_b <= ('0', '0', '0', '0', '0');
compare_signal <= '0';


else if (CLK_b = '1' and CLK_b'event) then


if (P_b = '1') then
Q_b <= Q_b+1;
compare_signal <= '0';

if (Q_b = data) then
compare_signal <= '1';
Q_b <= ('0', '0', '0', '0', '0');
end if;


end if;

--End If;
end if;
end if;
end process;
end count_arch_b;

thomas

Hello Thomas,

Thank you very much.

Regards
John.


thomas <> wrote in message


news:<clkpht$hiu$>...
> john wrote:
> > Hi thomas,
> > Thanks for ur reply! Would you please clear ur point more..
> > Thanks
> > Regards
> > john
>
> Hi John
>
> im not very good at VHDL but her it is
> if you want to clock the ser_buff data out you can use an index
> then index is the value of Q_b (see below in counter)
>
> the problem with you code,(I thing), is than you are making a glitch in
> state E1 when assigning new values to ser_buff(x)
>
> I made som changes to you code, i works for me know
>
>
> library IEEE;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
> entity P2S is
>
> port (
>
> parallel_in : in bit_vector (18 downto 0); -- Parallel
> Register,holds the 19- bits
> latch : in std_logic; -- When low, loads the data into the
> 19-bit register
> ds : in bit; -- Makes the parallel register shifts right
> or left
> ser_out : out bit; -- Serial data output pin
> CLK : in std_logic; -- Clock for the serial shift
> clk_out : out std_logic; -- Clock for the Digigtal to Analog
> converter
> synch : out std_logic; -- Synchronize the data frame
> cpld_ready : out std_logic
>
> );
> end P2S;
> architecture PISO_ARCH of P2S is
>
> --------------------------------------------
> component counter_b
> port (
> CLK_b : in std_logic;
> P_b : in std_logic;
> Load : in std_logic;
> index : out unsigned(4 downto 0);
> compare_signal : out std_logic
> );
> end component;
> -------------------------------------------------
> signal State : unsigned(3 downto 0);
> signal nextstate : unsigned(3 downto 0);
> constant E0 : unsigned(3 downto 0) := "0001";
> constant E1 : unsigned(3 downto 0) := "0010";
> constant E2 : unsigned(3 downto 0) := "0100";
> constant E3 : unsigned(3 downto 0) := "1000";
> --Signal SM_DIR : std_logic;
> -------------------------------------------------
> signal incrementB : std_logic;
> signal Load_counter : std_logic;
> signal compare : std_logic;
> ------------------------------------------------
> signal ser_buff : bit_vector (18 downto 0);
> signal index : unsigned(4 downto 0);
> signal xser_out : bit; -- temp signal
> begin
>
> -- remove glitch
> ser_out <= xser_out when compare = '0' and incrementB = '1' else '0';
>
> clk_out <= latch and clk;
> synch <= incrementB;
> cpld_ready <= compare;
>
> -- add index to counter
> CB : counter_b port map (CLK, incrementB, Load_counter, index, compare);
> --------------------------------------------------------------------------
> process(State, nextstate)
> begin
> case State is
>
> when E0 =>
> incrementB <= '0';
> --ser_buff <= "0101010101010101010";
> ser_buff <= parallel_in; -- take input from toplevel
> Load_counter <= '1';
> nextstate <= E1;
>
>
> when E1 =>
> if (compare = '0') then
> incrementB <= '1';
> Load_counter <= '0';
> xser_out <= ser_buff(to_integer(index));
> nextstate <= E1;
> else
>
> nextstate <= E0;
> end if;
>
>
>
> when others =>
> nextstate <= E0;
>
>
> end case;
>
> end process;
> --------------------------------------------------
> process (CLK)
> begin
> if (CLK'event and CLK = '1') then
> -- SM_DIR <= OE1;
> State <= nextstate;
>
> end if;
> end process;
> end PISO_ARCH;
>
>
> ----Counter------
>
> library IEEE;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
> ------------------------------------------------------------------
> entity counter_b is
> port (
>
> CLK_b : in std_logic;
> P_b : in std_logic;
> Load : in std_logic;
> index : out unsigned (4 downto 0);
> compare_signal : out std_logic
> );
> end counter_b;
> architecture count_arch_b of counter_b is
> signal Q_b : unsigned (4 downto 0);
> -- signal Q_b : natural range 0 to 13;
> signal data : unsigned (4 downto 0) := "10011";
> -- constant data : natural := 13;
> begin
>
> index <= Q_b; -- route Q_b to index
>
> process(CLK_b, Load)
>
> begin
>
> if (Load = '1')then
>
> Q_b <= ('0', '0', '0', '0', '0');
> compare_signal <= '0';
>
>
> else if (CLK_b = '1' and CLK_b'event) then
>
>
> if (P_b = '1') then
> Q_b <= Q_b+1;
> compare_signal <= '0';
>
> if (Q_b = data) then
> compare_signal <= '1';
> Q_b <= ('0', '0', '0', '0', '0');
> end if;
>
>
> end if;
>
> --End If;
> end if;
> end if;
> end process;
> end count_arch_b;

john