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VHDL - Problem simulating Xilinx CoreGenerator Cores with ModelSim SE 5.8C. |
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#1 |
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Hi.
I'm having issues simulating my design that uses a Xilinx CoreGenerator core. I imported the XilinxCoreLib directory, but ModelSim doesn't recognize the files as a library. Does anyone know if Xilinx provides a pre-compiled ModelSim library similar to those for unisim and simprim? Or, has anyone successfully simulated a Xilinx Core in VHDL, for example a fifo? Thanks, Jeremy Jeremy Webb |
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#2 |
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Yes, Xilinx has a simulation library for CoreGen. The quickest way to get
the correct answer would be to look on their web site. (I am at home and don't have quick access to the directory structure to tell you where to find what.) Actually, since it seems you've done the same thing with unisim and/or simprim, you should be able to find the source very quickly. Yhey are all in the same area; they all use the same command/script--just different arguments for the compile. Jason "Jeremy Webb" <> wrote in message news: om... > Hi. > > I'm having issues simulating my design that uses a Xilinx > CoreGenerator core. I imported the XilinxCoreLib directory, but > ModelSim doesn't recognize the files as a library. Does anyone know if > Xilinx provides a pre-compiled ModelSim library similar to those for > unisim and simprim? Or, has anyone successfully simulated a Xilinx > Core in VHDL, for example a fifo? > > Thanks, > > Jeremy jtw |
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#3 |
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(Jeremy Webb) wrote in message news:<. com>...
> Hi. > > I'm having issues simulating my design that uses a Xilinx > CoreGenerator core. I imported the XilinxCoreLib directory, but > ModelSim doesn't recognize the files as a library. Does anyone know if > Xilinx provides a pre-compiled ModelSim library similar to those for > unisim and simprim? Or, has anyone successfully simulated a Xilinx > Core in VHDL, for example a fifo? > > Thanks, > > Jeremy Hi. Nevermind. I figured it out. To be able to use the Xilinx Core's in ModelSim SE/PE you have to compile the XilinxCoreLib directory using COMPXLIB either from the command line or within ISE Project Navigator. The end result is a new directory with library information that ModelSim SE/PE can interpret. Once I did this, I was able to simulate all of my Xilinx cores correctly. Thanks, Jeremy Jeremy Webb |
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