64 bit counter with shift

Hi there,

I want to have a 64 bit counter, which overflows (return to 0) if it
reaches its limit. Also, I want to do some schift operations with this
counter.

My question is, if there is a predefined 64 bit type or if I have to
implement the counter manually with four integers (they are 16 bit wide,
aren't they?).
For the shifter: I don't have a specific device yet, and I wonder if the
compiler get it right with the "srl"-operator or if it is better to multiply
the value.

I am pretty new to vhdl, so hopefully this is quite easy to do..

And by the way, are there any online sources where I can view the contents
of the ieee-libraries?? If I search the IEEE-site I get too many hits.

Many thanks,
Stephan

Stephan Mueller

Stephan Mueller schrieb:
> Hi there,
>
> I want to have a 64 bit counter, which overflows (return to 0) if it
> reaches its limit. Also, I want to do some schift operations with this
> counter.
>
> My question is, if there is a predefined 64 bit type or if I have to
> implement the counter manually with four integers (they are 16 bit wide,
> aren't they?).
> For the shifter: I don't have a specific device yet, and I wonder if the
> compiler get it right with the "srl"-operator or if it is better to multiply
> the value.
>
> I am pretty new to vhdl, so hopefully this is quite easy to do..
>
> And by the way, are there any online sources where I can view the contents
> of the ieee-libraries?? If I search the IEEE-site I get too many hits.
>
> Many thanks,
> Stephan
>
>

Hi Stephan,

the easiest way might be the use of a std_logic_vector with 64 bits.
With vectors shifting becomes very easy.

Btw, as far as I know integers are 32 bits wide (at least Synopsys
synthesizes them to be 32 bits if you don't specify a range).

You can find the IEEE libraries on the website of the Hamburg VHDL library:

http://tech-www.informatik.uni-hamburg.de/vhdl/

They have links to several textbooks there as well (even in german

Regards,

Marcus

Marcus Schaemann

Stephan Mueller wrote:

> I want to have a 64 bit counter, which overflows (return to 0) if it
> reaches its limit.

Consider using unsigned. It overflows as default.

> Also, I want to do some schift operations with this counter.

ieee.numeric_std has shifts for unsigned.

> My question is, if there is a predefined 64 bit type or if I have to
> implement the counter manually with four integers (they are 16 bit wide,
> aren't they?).

Integers are often 32 bits.
Consider unsigned instead.

> For the shifter: I don't have a specific device yet, and I wonder if the
> compiler get it right with the "srl"-operator or if it is better to multiply
> the value.

Consider numeric_std.shift_left or numeric_std.sll

> I am pretty new to vhdl, so hopefully this is quite easy to do..

Once you know how to do it, it's quite easy.

> And by the way, are there any online sources where I can view the contents
> of the ieee-libraries?? If I search the IEEE-site I get too many hits.
see:
http://www.eda.org/vhdl-200x/vhdl-20...ges/files.html

-- Mike Treseler

Mike Treseler

Hi Marcus,

thanks for the link and I did it with a std_logic_vector..

Dankeschoen

Stephan

Stephan Mueller

"Stephan Mueller" <> wrote in message news:<>...
> Hi there,
>
> I want to have a 64 bit counter, which overflows (return to 0) if it
> reaches its limit. Also, I want to do some schift operations with this
> counter.
>
> My question is, if there is a predefined 64 bit type or if I have to
> implement the counter manually with four integers (they are 16 bit wide,
> aren't they?).
> For the shifter: I don't have a specific device yet, and I wonder if the
> compiler get it right with the "srl"-operator or if it is better to multiply
> the value.
>
> I am pretty new to vhdl, so hopefully this is quite easy to do..
>
> And by the way, are there any online sources where I can view the contents
> of the ieee-libraries?? If I search the IEEE-site I get too many hits.
>
> Many thanks,
> Stephan

I tried this with the QuartusII web edition and it compiled and fit an
APEX20K part. Didn't try and shifting operations.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port (
clock : in std_logic;
clear : in std_logic;
count : in std_logic;
Q : out std_logic_vector(63 downto 0)
);
end counter;

architecture behavorial of counter is
signal tempQ : std_logic_vector(63 downto 0);
begin
process(clock, clear, count)
begin
if clear='1' then
tempQ <= (others => '0');
elsif (clock'event and clock='1') then
if count = '1' then
tempQ <= tempQ + 1;
end if;
end if;
end process;
Q <= tempQ;
end behavorial;

Rob Young

Rob Young