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VHDL - Ones Counter

 
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Old 10-20-2004, 12:18 PM   #1
Default Ones Counter


Hello!

David Bishop wrote in this newsgroup a function which implemented a
recursive xor function. Please check out
http://groups.google.com/groups?hl=p...r.nyroc.rr.com

This worked beautifully in Synplify Pro 7.7. I tried extending the
idea to do a "Ones counter" using a generic binary adder structure.
The synthesis tool implements the function as if it was done in a FOR
loop and not recursively. I'm just curious as if somebody can
successfully use this function (get a binary adder tree) in another
synthesis tool or if there is a better way of doing this.
Thanks a lot. BTW, here is the code I adapted from Bishop's code.

function ones_count (arg : std_logic_vector )
return integer is
variable Upper, Lower : integer range 0 to VEC_SIZE;
variable Half : integer range 0 to VEC_SIZE;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : integer range 0 to VEC_SIZE;

begin
if (arg'LENGTH < 1) then -- In the case of a NULL
range
Result := 0;
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := conv_integer(BUS_int ( BUS_int'left ));
elsif ( BUS_int'length = 2 ) then
Result := conv_integer(BUS_int ( BUS_int'right )) +
conv_integer(BUS_int ( BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := ones_count ( BUS_int ( BUS_int'left downto Half ));
Lower := ones_count ( BUS_int ( Half - 1 downto
BUS_int'right));
Result := Upper + Lower;
end if;
end if;
return Result;
end;

Any ideas to make this work better? Thanks!

- Paulo Valentim


Paulo Valentim
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