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Hey Everyone,

Is this VHDL code valid:

sig_a <= sig_b when sig_c = '1';

when sig_c = '0' I want sig_a to keep its current value. Or must the when
clause always end with an else e.g.

sig_a <= sig_b when sig_c = '1' else '0';

TIA

Hans,
> Is this VHDL code valid:
>
> sig_a <= sig_b when sig_c = '1';

In VHDL-93 and beyond, yes.

It simulates as a latch (level sensitive storage) just
like you want. For synthesis, I would be cautious as
some synthesis tools may not support this. If you are
conservative, you would do well to use the equvalent
process:

process (sig_b, sig_c)
begin
if sig_c = '1' then
sig_a <= sig_b ;
end if ;
end process ;

The synthesis standard, 1076.6-2004 says compliant
synthesis tools must support this, so if you find
a tool that does not, kick them.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
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Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

> when sig_c = '0' I want sig_a to keep its current value. Or must the when
> clause always end with an else e.g.
>
> sig_a <= sig_b when sig_c = '1' else '0';
>
> TIA

The assignment you make is a combinational one
that is you need to register sig_a if you want to keep the value. For
that purpose you need a clock.

process(Clk)
begin
if rising_edge(Clk) then
sig_a <= sig_a; -- else tree of sic_c condition: you do not need
it here,
-- but it is good for visualization

if sig_c='1' then
sig_a <= sig_b;
end if;
end if;

end process;