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Addition of one

 
 
Julian
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      10-18-2004
Hi NG.

This is more a digital design related question, hope you have an idea.
Is there a fast way of adding one (1) to any number? Is there another way
than implementing an actual complete adder structure? Could this in some way
be reduced as we now have a fixed constant to add?

Best Regards
Julian


 
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Narendran Kumaraguru Nathan
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      10-18-2004
Julian wrote:
> Hi NG.
>
> This is more a digital design related question, hope you have an idea.
> Is there a fast way of adding one (1) to any number? Is there another way
> than implementing an actual complete adder structure? Could this in some way
> be reduced as we now have a fixed constant to add?
>
> Best Regards
> Julian
>
>


Hi,
The ieee packages "std_logic_arith", "std_logic_unsigned" &
"std_logic_signed" have overloaded the "+" operator. Hence you can just
add std_logic_vectors.
Thanks & Regards,
Naren.

Narendran Kumaraguru Nathan
TooMuch Semiconductor Solutions Pvt. Ltd.
www.toomuchsemi.com
A Bangalore based startup specialising on services in EDA & Verification.

 
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Narendran Kumaraguru Nathan
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      10-18-2004
Narendran Kumaraguru Nathan wrote:
> Julian wrote:
>
>> Hi NG.
>>
>> This is more a digital design related question, hope you have an idea.
>> Is there a fast way of adding one (1) to any number? Is there another way
>> than implementing an actual complete adder structure? Could this in
>> some way
>> be reduced as we now have a fixed constant to add?
>>
>> Best Regards
>> Julian
>>
>>

>
> Hi,
> The ieee packages "std_logic_arith", "std_logic_unsigned" &
> "std_logic_signed" have overloaded the "+" operator. Hence you can just
> add std_logic_vectors.
> Thanks & Regards,
> Naren.
>
> Narendran Kumaraguru Nathan
> TooMuch Semiconductor Solutions Pvt. Ltd.
> www.toomuchsemi.com
> A Bangalore based startup specialising on services in EDA & Verification.
>



Hi Julian,

I completely misunderstood the question and answered wrongly in a hurry.

Looking at the problem of addition, if you have one input constant,
the synthesis tool 'll be able to understand that and 'll make the
synthesised circuit much simpler. Also, if you can tell us your exact
problem... probably we can give you some suggestions on making the
circuit simpler ... & one that meets timing goals etc...

Thanks & Regards,
Naren.

Narendran Kumaraguru Nathan
TooMuch Semiconductor Solutions Pvt. Ltd.
www.toomuchsemi.com
A Bangalore based startup specialising on services in EDA & Verification.

 
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Jim Lewis
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      10-18-2004
Narendran Kumaraguru Nathan wrote:
> The ieee packages "std_logic_arith", "std_logic_unsigned" &
> "std_logic_signed" have overloaded the "+" operator.


Minor clarification:
Packages "std_logic_arith", "std_logic_unsigned" &
"std_logic_signed" are from Synopsys and are distributed
as free-ware. Hence they are well supported by many tools.
The fact that they were put in the ieee library is
contentious and some feel they should be removed - however -
many others agree it is contentious, they do not
see any value in breaking old code.


Package numeric_std is the recommended IEEE package
for new designs. It also overloads addition to allow
use of integers with unsigned/signed.

On the standard horizon, there will be a numeric_unsigned
package from IEEE, however, there will not be a
numeric_signed package.

Like Narendran stated in his follow-up email, optimization of
the addition of an unsigned/signed with a constant integer
value (or a constant value of type unsigned/signed) will be
appropriately handled by synthesis tools.

Regards,
Jim
--
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Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

 
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rickman
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      10-19-2004
Julian wrote:
>
> Hi NG.
>
> This is more a digital design related question, hope you have an idea.
> Is there a fast way of adding one (1) to any number? Is there another way
> than implementing an actual complete adder structure? Could this in some way
> be reduced as we now have a fixed constant to add?


There is no magic reduction that adding a constant will provide. But in
an FPGA the circuit is a bit simpler than adding two variable numbers.
Adding one only requires a series of half adders vs. a chain of full
adders. You still need a LUT for each bit, but you have some free
inputs to the LUT that can be used to add other functions such as a mux,
load or clear control.

--

Rick "rickman" Collins

http://www.velocityreviews.com/forums/(E-Mail Removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
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Nicolas Matringe
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      10-19-2004
Jim Lewis a écrit:

> On the standard horizon, there will be a numeric_unsigned
> package from IEEE, however, there will not be a
> numeric_signed package.


Maybe I am not an advanced user enough but I can't see what's missing in
numeric_std that would need the addition of a new package.


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Paul Uiterlinden
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      10-19-2004
Nicolas Matringe wrote:
> Jim Lewis a écrit:
>
>> On the standard horizon, there will be a numeric_unsigned
>> package from IEEE, however, there will not be a
>> numeric_signed package.

>
>
> Maybe I am not an advanced user enough but I can't see what's missing in
> numeric_std that would need the addition of a new package.


The arithmetic operators are overloading only for types signed and
unsigned, not for std_logic_vector. The latter was done in package
ieee.std_logic_unsigned (by Synopsys, not IEEE).

Though this was convenient, it is actually not allowed to overload an
operator (e.g. "=") in another package (std_logic_unsigned) than where
it originally was defined (std_logic_1164, which impicitely defines an
"=" operator with the declaration of the std_logic type). Hence the
"-explicit" option in ModelSim to allow the non LRM compliant code.

With ieee.std_logic_(un)signed, you cannot mix signed and unsigned
operations in one design unit using those packages.

With ieee.numeric_std you can, because you always have to use the types
signed or unsigned for arithmetic operation on vectors.

When using an arithmetic operation on a std_logic_vector, some
conversions back and forth must be used, making the code quite lengthy:

VARIABLE a: std_logic_vector(7 DOWNTO 0);

a := std_logic_vector(unsigned(a) + 1);

That's why I think people are asking for numeric_unsigned, making it
possible to write "a := a + 1;" again.

Of course, changing the type of "a" to unsigned(7 DOWNTO 0) would
accomplish the same, but you will need a conversion again when assigning
"a" to a std_logic_vector.

Paul.
 
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Nicolas Matringe
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      10-19-2004
Paul Uiterlinden a écrit:

> When using an arithmetic operation on a std_logic_vector, some
> conversions back and forth must be used, making the code quite lengthy:
>
> VARIABLE a: std_logic_vector(7 DOWNTO 0);
>
> a := std_logic_vector(unsigned(a) + 1);
>
> That's why I think people are asking for numeric_unsigned, making it
> possible to write "a := a + 1;" again.
>
> Of course, changing the type of "a" to unsigned(7 DOWNTO 0) would
> accomplish the same, but you will need a conversion again when assigning
> "a" to a std_logic_vector.


So this would only allow arithmetic operations on std_logic_vector?
Really no point, IMO

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Paul Uiterlinden
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      10-19-2004
Nicolas Matringe wrote:
> Paul Uiterlinden a écrit:
>> Of course, changing the type of "a" to unsigned(7 DOWNTO 0) would
>> accomplish the same, but you will need a conversion again when
>> assigning "a" to a std_logic_vector.

>
> So this would only allow arithmetic operations on std_logic_vector?


I'm not sure what you mean here. Operators are overloaded, so integers
(and reals) would work too.

Paul.
 
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Nicolas Matringe
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      10-19-2004
Paul Uiterlinden a écrit:

>> So this would only allow arithmetic operations on std_logic_vector?

> I'm not sure what you mean here. Operators are overloaded, so integers
> (and reals) would work too.


I meant that the purpose of this overloading is to add the possibility
of doing arithmetic operation on std_logic_vector.
I know integers and so on are still supported, as they are with numeric_std.
I don't see the point of adding such a support. Type casting may be
tedious but it is much cleaner.

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