«

Hi
I have just started to learn VHPI.
I met lot of problems when I tried to interface a C code with the VHDl.
I have a small Transmitter design as

entity uart_tx is
port (
clk16: in STD_LOGIC;
async_reset: in STD_LOGIC;
data: in STD_LOGIC_VECTOR (7 downto 0);
data_size: in STD_LOGIC_VECTOR (2 downto 0);
send_data: in STD_LOGIC;
parity_type: in STD_LOGIC;
tx: out STD_LOGIC;
busy: out STD_LOGIC
);
end uart_tx;

Whenever clk16 is high, If input send_data is high, the design should
take the 'data[data_size]' input and deliver output via 'tx' one bit per
cycle with start bit('0') and end with parity bit & stop bit('1').

This is what my requirement. I have done this in Verilog using PLI.

But here I feel difficult.

Any one give better solution for this and give better link/book to learn
VHPI.

by
karthikeyan
TooMuch Semiconductor Solutions.,
Bangalore.