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generics in vhdl

 
 
nachzeher
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      10-11-2004
hello, i hope u can help me... i want to know if it's possible that
generics ports can change the default value assigned in the vhdl code when
i compile or i program... better said, what can i do with generics ports?
what are they useful for?

 
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Narendran Kumaraguru Nathan
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      10-12-2004
nachzeher wrote:
> hello, i hope u can help me... i want to know if it's possible that
> generics ports can change the default value assigned in the vhdl code when
> i compile or i program... better said, what can i do with generics ports?
> what are they useful for?
>


The answer to the first question depends on the compiler you use.
For modelsim there is an option "-G" in VCS the option is "-generic".
Better take a look at your compiler's user manual.

Generics in VHDL are used to construct parameterized hardware
components. Parameterized components make it possible to construct
standardized libraries of shared models.

The following links should help you understand

http://www.orcadpcb.com/kb_articles/cap02921.asp?bc=F
http://www.emba.uvm.edu/~jswift/uvm_.../generics.html


Narendran Kumaraguru Nathan
TooMuch Semiconductor Solutions Pvt. Ltd.
www.toomuchsemi.com
A Bangalore based startup specialising on services in EDA & Verification.

 
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Narendran Kumaraguru Nathan
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Posts: n/a
 
      10-12-2004
"nachzeher" <(E-Mail Removed)> wrote in message news:<(E-Mail Removed) alkaboutprogramming.com>...
> hello, i hope u can help me... i want to know if it's possible that
> generics ports can change the default value assigned in the vhdl code when
> i compile or i program... better said, what can i do with generics ports?
> what are they useful for?


The answer to the first question depends on the compiler you use.
For modelsim there is an option "-G" in VCS the option is "-generic".
Better take a look at your compiler's user manual.

Generics in VHDL are used to construct parameterized hardware
components. Parameterized components make it possible to construct
standardized libraries of shared models.

The following links should help you understand

http://www.orcadpcb.com/kb_articles/cap02921.asp?bc=F
http://www.emba.uvm.edu/~jswift/uvm_.../generics.html


Narendran Kumaraguru Nathan
TooMuch Semiconductor Solutions Pvt. Ltd.
www.toomuchsemi.com
A Bangalore based startup specialising on services in EDA &
Verification.
 
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Moti Cohen
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Posts: n/a
 
      10-12-2004
"nachzeher" <(E-Mail Removed)> wrote in message news:<(E-Mail Removed) alkaboutprogramming.com>...
> hello, i hope u can help me... i want to know if it's possible that
> generics ports can change the default value assigned in the vhdl code when
> i compile or i program... better said, what can i do with generics ports?
> what are they useful for?


The web is loaded with tutorial expalining this subject but since u
asked I'll try to explain

Generics are used in order for u to be able to declare constants in
the design in a generic way e.g. -

entity adder is
generic (bus_width : integer := ;
Port ( a: in std_logic_vecor (bus_width-1 downto 0);
b: in std_logic(bus_width-1 downto 0);
res : out std_logic(bus_width downto 0));
end adder ;

architecture bhv of adder is
begin

process (a,b,res)
begin
res <= a + b;
end process;

end bhv;

in the example above the adder can be instantiated with the required
bus width just by setting the "bus_width" generic.
 
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vipinlal vipinlal is offline
Member
Join Date: Feb 2010
Posts: 39
 
      03-10-2010
this may help you..
vhdlguru.blogspot.com/2010/03/generics-in-vhdl-construction-of.html
 
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somayeh2010 somayeh2010 is offline
Junior Member
Join Date: Sep 2010
Posts: 1
 
      09-09-2010
Quote:
Originally Posted by vipinlal
this may help you..
vhdlguru.blogspot.com/2010/03/generics-in-vhdl-construction-of.html
help me!!!!!!!!!!!!!!!!!!!1
I design a n_bit register and in the design I use dffs (with use of port map and generic map). Also I write a package and I put all of my component declarations in it. Now I want write a test bench for this register. But my test bench has error, and doesn't know my generic variable.
--package declaration
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

PACKAGE basic_utility IS

COMPONENT dff
PORT(din,clk,rst:IN std_logic;
dout:OUT std_logic);
END COMPONENT;

COMPONENT reg_nb
GENERIC (length:natural);
PORT(reg_in:IN std_logic_vector(length DOWNTO 0);
clk,rst:IN std_logic;
reg_out:OUT std_logic_vector(length DOWNTO 0));
END COMPONENT;
END basic_utility;

--dff
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY dff IS
PORT(din,clk,rst:IN std_logic;
dout:OUT std_logic);
END dff;

ARCHITECTURE behavioral OF dff IS
BEGIN
process(clk)
BEGIN
IF (rst= '1')THEN
dout<='0';
ELSE
IF (clk='1' AND clk'event) THEN
dout<=din;
END IF;
END IF;
END PROCESS;

END behavioral;

--n bit register
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.basic_utility.ALL;

ENTITY reg_nb IS
GENERIC (length:natural);
PORT(reg_in:IN std_logic_vector(length DOWNTO 0);
clk,rst:IN std_logic;
reg_out:OUT std_logic_vector(length DOWNTO 0));
END reg_nb;

ARCHITECTURE structural OF reg_nb IS
BEGIN
reg:
FOR i IN length DOWNTO 0 GENERATE
DFF_units:dff
PORT MAP(din=>reg_in(i),clk=>clk,rst=>rst,dout=>reg_out (i));
END GENERATE;
END structural;

--test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.basic_utility.ALL;

ENTITY reg_nb_test IS
END reg_nb_test;

ARCHITECTURE test OF reg_nb_test IS

SIGNAL r_in: std_logic_vector(length DOWNTO 0);
SIGNAL r_out: std_logic_vector(length DOWNTO 0);
SIGNAL clk: std_logic :='0';
SIGNAL rst: std_logic:='1';

BEGIN
--Generate clock
clk<=NOT clk AFTER 10 ns;
rst<='0' AFTER 3ns;
r_in<="11110000" AFTER 15 ns;
reg1:reg_nb
GENERIC MAP(length=>7) PORT MAP(reg_in=>r_in,clk=>clk,rst=>rst,reg_out=>r_out) ;

END test;
 
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joris joris is offline
Senior Member
Join Date: Jan 2009
Posts: 152
 
      09-10-2010
Length is not declared in the architecture of reg_nb_test; You must declare
a constant for it.

Code:
ARCHITECTURE test OF reg_nb_test IS
constant length : natural := 7;
SIGNAL r_in: std_logic_vector(length DOWNTO 0);
SIGNAL r_out: std_logic_vector(length DOWNTO 0);
SIGNAL clk: std_logic :='0';
SIGNAL rst: std_logic:='1';

BEGIN
--Generate clock
clk<=NOT clk AFTER 10 ns;
rst<='0' AFTER 3ns;
r_in<="11110000" AFTER 15 ns;
reg1:reg_nb
GENERIC MAP(length=>7) PORT MAP(reg_in=>r_in,clk=>clk,rst=>rst,reg_out=>r_out) ;

END test;
Also, even if apparently using 'length' as a variable/generic name is allowed, I would prefer using a name that isn't also a VHDL keyword; it's likely to confuse readers, and it does confuse syntax highlighters
 
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mink mink is offline
Junior Member
Join Date: Nov 2010
Posts: 1
 
      11-23-2010
Can a generic be used to compute a compile time signal value, if so how ?
I'm passing a generic width for signal sizing, but I also want to initialize
a counter based on that value.

entity gen_keys is
generic (
key_size : integer := 16 -- bits of key & cntr value
);
Port (
clk :in std_logic;
reset :in std_logic;
new_seed :in std_logic;
fifo_full :in std_logic;
wrt_key ut std_logic;
key_out ut std_logic_VECTOR(key_size-1 downto 0)

);
end gen_keys;

architecture Behavioral of gen_keys is

signal cntr : std_logic_VECTOR(11 downto 0);

begin

cntr <= x"480"/key_size;

end Behavioral;
 
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