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....sorry if this has already been discussed before but i didnt get
nething addressing my exact concern on searching the archives! ...or
was i just too lazy!!
so here goes! I have multiple processes within an architecture of a
VHDl entity that writes to common signals. I understand that this is a
case of multiple drivers and that it is incorrect to have two
processes drive diff values on the signals simultaneously.
but i precisely know how my process executions overlap and am sure
that no two process will drive values at the same time. As in, if one
drives either 0 or 1 on the signal, all others are definitely driving
a 'Z' (or basically tristated).
....and yes it is important for me to keep them as separate processes
and not combine them into a single big process.

How do i pass on this information to the synthesizer to allow it to
complete sythesis process without errors? I am using Xilinx 6.3i for
FPGA syntheis.

Lemme know if u would like to see the code or need more details.

Thanks
Hakim

hakim wrote:

> so here goes! I have multiple processes within an architecture of a
> VHDl entity that writes to common signals. I understand that this is a
> case of multiple drivers and that it is incorrect to have two
> processes drive diff values on the signals simultaneously.
> but i precisely know how my process executions overlap and am sure
> that no two process will drive values at the same time. As in, if one
> drives either 0 or 1 on the signal, all others are definitely driving
> a 'Z' (or basically tristated).

A tri-state driver is described with:

process(enable,data_in)
begin
if (enable='1') then
data_out<=data_in;
else data_out<=(others=>'Z');
end if;
end process;

Make it easy for the synthesis tool and use this tri-state description
explictly. (In other words: write in a biger process to a dummy signal
(data_in) and gate this dummy signal in an extra tri-state driver.)

data_out must be a resolved data type (std_logic(_vector)). You may
write to data_out from many tri-state describing processes.

Make sure, that your target supports tri-state drivers.

Ralf

On 9 Oct 2004 21:50:47 -0700, (hakim) wrote:

>...sorry if this has already been discussed before but i didnt get
>nething addressing my exact concern on searching the archives! ...or
>was i just too lazy!!
> so here goes! I have multiple processes within an architecture of a
>VHDl entity that writes to common signals. I understand that this is a
>case of multiple drivers and that it is incorrect to have two
>processes drive diff values on the signals simultaneously.
>but i precisely know how my process executions overlap and am sure
>that no two process will drive values at the same time. As in, if one
>drives either 0 or 1 on the signal, all others are definitely driving
>a 'Z' (or basically tristated).
>...and yes it is important for me to keep them as separate processes
>and not combine them into a single big process.
>
>How do i pass on this information to the synthesizer to allow it to
>complete sythesis process without errors? I am using Xilinx 6.3i for
>FPGA syntheis.

#disclaimer: still learning but having fun

AFAIK, the only way to do this is to have the "single big process" that
you say you don't want. Not sure otherwise how to explicitly control
which gets to change what, when.

...
big_signal : std_logic;
...
big_signal <= this_event or that_event or other_event or ... ;
...
process (reset, big_signal)
...
if reset = '0'
...
elsif big_signal'event and big_signal = '1'
if this_event = '1'
...

and so on.

--
Rich Webb Norfolk, VA

hakim wrote:

> that no two process will drive values at the same time. As in, if one
> drives either 0 or 1 on the signal, all others are definitely driving
> a 'Z' (or basically tristated).

Use a mux structure to combine your outputs
in a single process. FPGAs of recent vintage
do not allow internal tri-state nodes.

-- Mike Treseler