Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Edge Detection circuit.

Reply
Thread Tools

Edge Detection circuit.

 
 
Pieter Hulshoff
Guest
Posts: n/a
 
      10-10-2004
Eric Smith wrote:
>> That's how the pulse-triggered flip-flops worked, but that technique has
>> not been in common use for a long time. It is not truly edge-sensitive,
>> because it is sensitive to input changes during the entire low period of
>> the clock, not just a narrow window near the rising edge.


Could we please all use the same terminology? A pulse (level) triggered
memory device is usually called a latch. An edge triggered memory device is
usually called a flip-flop.

> Unfortunately the authors do not explain the construction of such
> a device, though the 7474 and 74109 are real-world examples of it.


The idea of a FF that isn't partial to meta-stability is nice, but in
general not affordable within ASICs or FPGAs. That's why we have to be very
careful when signals cross clock boundaries.

>> The 7474 is a slightly tricky master-slave circuit.

>
> The 7474 is not a master-slave flip-flop. It actually contains three
> S-R flip-flops in a non-obvious configuration, very much unlike what
> Paul Uiterlinden described.


I'm not familiar with the 7474, but I know that constructions with 3 latches
in sequence are sometimes used when transferring signals over a larger
distance. It creates, in some situations, a better clock data relation at
the receiving FF.

Regards,
Pieter Hulshoff

 
Reply With Quote
 
 
 
 
Mike Treseler
Guest
Posts: n/a
 
      10-10-2004
rickman wrote:

> I'm not clear why you say it is "sensitive" to input changes in the low
> clock period. The input can change many times while the clock is low,
> but only the last state of the input before the clock rises will be
> remembered by the first latch and therefore by the second latch which is
> the output.


I agree. The master latch(mux) is enabled by the constant clock.
The data setup requirement is to the rising edge, where
the slave latch(mux) is enabled. This is exactly how the
Actel ACT1 devices made D-flops.

-- Mike Treseler
 
Reply With Quote
 
 
 
 
Mike Treseler
Guest
Posts: n/a
 
      10-10-2004
Eric Smith wrote:

> Quoting from "The Art of Digital Design" by Prosser and Winkel,
> Second Edition, Chapter 4:
>
> The master-slave flip-flop appears to be an attractive edge-driven
> device. Why are we not content with this design? Because the
> master flip-flop is still a 1's catcher during the positive half
> of the clock cycle.


They are either talking about a different circuit, or they
got it wrong. The master latch(mux) follows the D input
input, but the only "catching" behavior is at the rising
clock edge when the master data passes to the slave latch(mux).

-- Mike Treseler

 
Reply With Quote
 
Eric Smith
Guest
Posts: n/a
 
      10-10-2004
Pieter Hulshoff <(E-Mail Removed)> writes:
> Could we please all use the same terminology? A pulse (level) triggered
> memory device is usually called a latch. An edge triggered memory device is
> usually called a flip-flop.


The book I was quoting distinguishes between level-triggered (latch),
pulse-triggered (master-slave), and edge-triggered. Sorry, I don't know
what better terminology to use to describe it.

The point was that the behavior of a master-slave FF is NOT always
the same as that of an edge-triggered FF. This is why master-slave FFs
went out of style in the late 1970s.

> The idea of a FF that isn't partial to meta-stability is nice, but in


That's not what they're talking about, and it's not even theoretically
possible to eliminate metastability.

>> The 7474 is not a master-slave flip-flop. It actually contains three
>> S-R flip-flops in a non-obvious configuration, very much unlike what
>> Paul Uiterlinden described.

>
> I'm not familiar with the 7474, but I know that constructions with 3 latches
> in sequence are sometimes used when transferring signals over a larger
> distance. It creates, in some situations, a better clock data relation at
> the receiving FF.


The 7474 does NOT have three in sequence. It has two SR flops in the
first stage, and one in the second. There's no easy way to explain it,
which is why I referenced the diagram in the TI data sheet.

 
Reply With Quote
 
Pieter Hulshoff
Guest
Posts: n/a
 
      10-10-2004
Eric Smith wrote:
>> Could we please all use the same terminology? A pulse (level) triggered
>> memory device is usually called a latch. An edge triggered memory device
>> is usually called a flip-flop.

>
> The book I was quoting distinguishes between level-triggered (latch),
> pulse-triggered (master-slave), and edge-triggered. Sorry, I don't know
> what better terminology to use to describe it.


It seems I could have used a bit of reading up on my knowledge as well.
Might be a language thing too (I'm Dutch. It appears in literature a
difference is made between level sensitive (Latch), and level triggered
(AKA pulse triggered). There are indeed two different types of FFs: pulse
triggered and edge triggered.

> The point was that the behavior of a master-slave FF is NOT always
> the same as that of an edge-triggered FF. This is why master-slave FFs
> went out of style in the late 1970s.


From what I could find, and it can also be found in the lecture Paul
Uiterlinden wrote about, it's the pulse triggered FF that has the problem
you described, and AFAIK the pulse triggered FF that went out of style.
This is also what I believe Mike Treseler said in a previous post.

> That's not what they're talking about, and it's not even theoretically
> possible to eliminate metastability.


True, but it's possible to create circuits that properly take signals from
one clock area to the next, despite metastability.

> The 7474 does NOT have three in sequence. It has two SR flops in the
> first stage, and one in the second. There's no easy way to explain it,
> which is why I referenced the diagram in the TI data sheet.


I just had a look at the datasheet (my apologies for not doing so before
posting). From what I can tell that device contains 2 FFs, each edge
triggered, and each having an asynchronous set and reset. The asynchronous
set/reset is why they need 3 latches i.s.o. 2.

Regards,

Pieter Hulshoff

 
Reply With Quote
 
Ken Smith
Guest
Posts: n/a
 
      10-10-2004
In article <(E-Mail Removed)>,
Eric Smith <(E-Mail Removed)> wrote:
[...]
> device. Why are we not content with this design? Because the
> master flip-flop is still a 1's catcher during the positive half
> of the clock cycle. This means that R and S must stabilize during
> the negative half of the clock, since the master flip-flop will
> react to any T glitches during the positive clock phase.



They are either (a) speaking of a different cicruit than the common
master-slave flip-flip or (b) wrong.

If you want to see a schematic that is easier to understand, look at the
CD4013's data sheet. It is much less tricky in how things are done.

The master section of the master-slave circuit followes its input when the
clock is low. Its output drives the input of the slave section. The
slave section follows its input when the clock is high. Whatever state
the master section is in, will appear at the output just after the rising
edge of the clock and remain there until the next rising edge of the
clock.

>Unfortunately the authors do not explain the construction of such
>a device, though the 7474 and 74109 are real-world examples of it.


Take a very careful look at the 7474's schematic. You will discover that
it is just a funny sort of master-slave design.

>
>Metastability is not explained until Chapter 12.
>
>> The 7474 is a slightly tricky master-slave circuit.

>
>The 7474 is not a master-slave flip-flop. It actually contains three
>S-R flip-flops in a non-obvious configuration, very much unlike what
>Paul Uiterlinden described.


I'm looking at the transistor level schematic of the 7474. There are two
and only 2 flip-flops in the transistor level schematic. Its in the data
sheet. Take a look. There are a cross coupled pair near the bottom of
the page forming the master and a more complex slave above it.

If you look at the "logic diagram" you will see that the uppermost
flip-flip takes the PRE/ and CLR/ as inputs. In the transistor schematic
that part is replaced by some simple stearing logic that does not involve
feedback.

--
--
http://www.velocityreviews.com/forums/(E-Mail Removed) forging knowledge

 
Reply With Quote
 
Ken Smith
Guest
Posts: n/a
 
      10-10-2004
In article <4168e663$0$30036$(E-Mail Removed)4all.n l>,
Pieter Hulshoff <(E-Mail Removed)> wrote:
[...]
>Could we please all use the same terminology? A pulse (level) triggered
>memory device is usually called a latch. An edge triggered memory device is
>usually called a flip-flop.


I'm using:

In the following, you can exchange "high" with "low" and get the neg.
polarity version.

The "D" input is the data input to the flip-flip

"edge-triggered" means that the output takes on the logic value that was
at the "D" input when the clock went from low to high and remains that way
until the next time the clock goes from low to high.


"pulse" "level triggered" and "latch" all refer to circuits where the
output either (a) follows the input or (b) is not useful while the clock
is high and holds the value when the clock is low. In most cases, the
output follows the input but the (b) case can also be true.


>I'm not familiar with the 7474, but I know that constructions with 3 latches
>in sequence are sometimes used when transferring signals over a larger
>distance. It creates, in some situations, a better clock data relation at
>the receiving FF.


The 3rd flip-flop in the "logic diagram" handles stearing of the PRE/ and
CLR/ signals it is in parallel with the main master/slave pair.

When dealing with signals coming in from the outside, it is common to put
a couple or 3 flip-flops in the path with a bit of logic around them.
These circuits, lower the odds of a glitch at the output at the cost of a
delay to the input signal. A M.S. state on the first stage has to remain
for a whole clock cycle to cause trouble. The odds of that are quite low.

--
--
(E-Mail Removed) forging knowledge

 
Reply With Quote
 
digitalpbk digitalpbk is offline
Junior Member
Join Date: Jun 2009
Posts: 1
 
      06-30-2009
Image Edges can be detected using FPGA project (edge.kitiyo.com)

Edges on signals can be detected using a high pass RC circuit.
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Lenovo ThinkPad EDGE 13: Bleeding Edge Ian Front Page News 0 02-28-2011 10:18 AM
using both rising edge and falling edge of signal denish VHDL 5 11-17-2008 07:12 PM
false edge detection apurva VHDL 1 08-18-2006 03:52 PM
Boost.graph - changing edge end-points or copying an edge Ferdi Smit C++ 0 10-10-2005 04:30 PM
edge detection using subprograms M.Randelzhofer VHDL 6 02-09-2005 01:23 AM



Advertisments