«

hi,

I have a question regarding inserting delays for signals in design. I
know that there are these transport delay statements to specify
certain time. But I believe they are not synthesizable and won't
produce the same result after implementing onto any FPGA.Is there any
way to set delays on signals in design to get the exact synthesized
result?

Thanks
V.N

Viswan wrote:
> I have a question regarding inserting delays for signals in design. I
> know that there are these transport delay statements to specify
> certain time. But I believe they are not synthesizable and won't
> produce the same result after implementing onto any FPGA.Is there any
> way to set delays on signals in design to get the exact synthesized
> result?

No, not really. The best you can hope for is by instantiating a specific
component of which you can predict the delay, but even that delay will vary
with temperature, power, etc. What did you want to use it for anyway?

Regards,

Pieter Hulshoff

Pieter Hulshoff <> wrote in message news:<416461f5$0$130$4all .nl>...
> Viswan wrote:
> > I have a question regarding inserting delays for signals in design. I
> > know that there are these transport delay statements to specify
> > certain time. But I believe they are not synthesizable and won't
> > produce the same result after implementing onto any FPGA.Is there any
> > way to set delays on signals in design to get the exact synthesized
> > result?
>
> No, not really. The best you can hope for is by instantiating a specific
> component of which you can predict the delay, but even that delay will vary
> with temperature, power, etc. What did you want to use it for anyway?
>
> Regards,
>
> Pieter Hulshoff


I am designing a hardware unit that can be used as an interface to a
sensor and the FPGA on which my rest of the hardware exists. I have
to generate some synchronizing clock signals at certain delays, to
start the communication.

for example 2 siignals are needed to be sent to sensor as follows.
data is bidirectional.

data <---> ----| |-------
|----------|
|-----| |----|
sclk <---- --| |----| |-----

I thought it would be better if I could generate it using delays..
ANother idea I have in my mind is to use counters and generate these
waveforms. But i doubt if there is any other good idea for this.

Thanks a lot.

Viswan wrote:

> I am designing a hardware unit that can be used as an interface to a
> sensor and the FPGA on which my rest of the hardware exists. I have
> to generate some synchronizing clock signals at certain delays, to
> start the communication.
>
> for example 2 siignals are needed to be sent to sensor as follows.
> data is bidirectional.
>
> data <---> ----| |-------
> |----------|
> |-----| |----|
> sclk <---- --| |----| |-----
>
> I thought it would be better if I could generate it using delays..
> ANother idea I have in my mind is to use counters and generate these
> waveforms. But i doubt if there is any other good idea for this.

Do you have any information on how stable your clock should be? I think it's
probably wisest to put a clock crystal on your board, and either use that
clock or derive a clock from that clock. Creating one directly from logic
within your FPGA will most likely not give you a workable clock, unless you
have a very very loose timing specification.

Regards,

Pieter Hulshoff

Viswan wrote:

> I am designing a hardware unit that can be used as an interface to a
> sensor and the FPGA on which my rest of the hardware exists. I have
> to generate some synchronizing clock signals at certain delays, to
> start the communication.
>
> for example 2 siignals are needed to be sent to sensor as follows.
> data is bidirectional.
>
> data <---> ----| |-------
> |----------|
> |-----| |----|
> sclk <---- --| |----| |-----
>
> I thought it would be better if I could generate it using delays..
> ANother idea I have in my mind is to use counters and generate these
> waveforms. But i doubt if there is any other good idea for this.


Hello,

I remember your post about the SHT7x, and thought this piece of code might
help you:

library ieee ;
use ieee.std_logic_1164.all ;

entity driver is
port (
rstb : in std_logic; -- Reset Active Low
clk : in std_logic; -- Clk Input
SCK : out std_logic; -- SCK
DATA : inout std_logic -- DATA
) ;
end driver ;

architecture rtl of driver is

begin
main : process (rstb, clk)
type state_t is (
idle,
start1,start2,start3,start4,start5,start6,
address1, --to be continued
ack1, --to be continued
waiting --to be continued
);
variable state : state_t;

begin
if rstb = '0' then
state := idle;
DATA <= 'Z';
SCK <= '0';
elsif clk'event and clk='1' then
case state is
when idle =>
state := start1;
when start1 =>
DATA <= '1';
SCK <= '1';
state := start2;
when start2 =>
DATA <= '0';
SCK <= '1';
state := start3;
when start3 =>
DATA <= '0';
SCK <= '0';
state := start4;
when start4 =>
DATA <= '0';
SCK <= '1';
state := start5;
when start5 =>
DATA <= '1';
SCK <= '1';
state := start6;
when start6 =>
DATA <= '1';
SCK <= '0';
state := address1;
when others =>
--to be continued
end case;
end if;
end process main;


If you need further help, contact me through e-mail, why is yours not working?

TechCon

(Viswan) wrote in message
>
> I am designing a hardware unit that can be used as an interface to a
> sensor and the FPGA on which my rest of the hardware exists. I have
> to generate some synchronizing clock signals at certain delays, to
> start the communication.
>
> for example 2 siignals are needed to be sent to sensor as follows.
> data is bidirectional.
>
> data <---> ----| |-------
> |----------|
> |-----| |----|
> sclk <---- --| |----| |-----
>
> I thought it would be better if I could generate it using delays..
> ANother idea I have in my mind is to use counters and generate these
> waveforms. But i doubt if there is any other good idea for this.
>
> Thanks a lot.

The best way to do this is to drive the data on the falling edge of
the clock so the the data is interpreted by the sensor on the rising
edge.

If the clock is too fast, then the best way is, like somebody already
said, to use a crystal or internal FPGA PLL. Then you would use (if
clock'falling_edge) expression.

If the clock is slow enough then it can be generated using logic with
the FPGA.

Take care,

- Paulo Valentim