Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Initial Value at start of process

Reply
Thread Tools

Initial Value at start of process

 
 
Roger Planger
Guest
Posts: n/a
 
      10-05-2004
Hi

I have declared a Type with different states as you can see.

type STATE_TYPE is (IDLE, STLDA, STLDB, ADDS, FINISHS);

My question now is, how can I say my VHDL compiler that when he starts we
are in the IDLE State? Afterwards
it is easy to jump from one state to another.

Thanks for any hints

R


 
Reply With Quote
 
 
 
 
Roger Planger
Guest
Posts: n/a
 
      10-05-2004
Sorry for this stupid question, I figured it out in the meantime

Cheers


 
Reply With Quote
 
 
 
 
valentin tihomirov
Guest
Posts: n/a
 
      10-05-2004
> Sorry for this stupid question, I figured it out in the meantime

Actually, it is not. Meantime I was sure that initialization during
declaration
signal STATE: TENUM := IDLE;

is intended for simulation while synthesis style must be:

process(CLK, RST)
if ASYNC_RST and RST = '1'
STATE <= IDLE;
else if Rising_Edge(CLK)
if not ASYNC_RST and RST = '1' then
STATE <= IDLE;

It turns out that the redundancy is needed as Xilinx FPGA loader will
initialize FFs to the values found in the declaration section.


 
Reply With Quote
 
Roger Planger
Guest
Posts: n/a
 
      10-06-2004
Hi

THanks for this hint, my problem is that I dont have a reset signal at the
moment. Therefore I want my State Machine to
be in the Idle state right from the beginning. It looks like that I have to
add this reset port to my IP

cheers

Roger

"valentin tihomirov" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
>> Sorry for this stupid question, I figured it out in the meantime

>
> Actually, it is not. Meantime I was sure that initialization during
> declaration
> signal STATE: TENUM := IDLE;
>
> is intended for simulation while synthesis style must be:
>
> process(CLK, RST)
> if ASYNC_RST and RST = '1'
> STATE <= IDLE;
> else if Rising_Edge(CLK)
> if not ASYNC_RST and RST = '1' then
> STATE <= IDLE;
>
> It turns out that the redundancy is needed as Xilinx FPGA loader will
> initialize FFs to the values found in the declaration section.
>
>



 
Reply With Quote
 
Pieter Hulshoff
Guest
Posts: n/a
 
      10-06-2004
Roger Planger wrote:
> THanks for this hint, my problem is that I dont have a reset signal at the
> moment. Therefore I want my State Machine to
> be in the Idle state right from the beginning. It looks like that I have
> to add this reset port to my IP


I believe that within an FPGA you can make sure the design starts in a
defined state. For an ASIC however this is not possible. As such it is good
practice to place a reset within your design, and if I may be so bold:
please make it a synchronous reset i.s.o. an asynchronous one...

Regards,

Pieter Hulshoff

 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Process.Start... started process not executing any code jpock76 ASP .Net 0 08-23-2010 02:16 PM
initial value of pointer value in std map ? PGK C++ 1 04-02-2009 10:46 AM
PROCESS.START Help - Need to start app that listens on a port Lucas Tam ASP .Net 0 06-17-2005 02:09 PM
A process serving application pool 'DefaultAppPool' exceeded time limits during start up. The process id was '216'. jack ASP .Net 0 08-01-2004 09:49 PM



Advertisments