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Synthesizable (kind of) dual-edge FF

 
 
Nicolas Matringe
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      09-27-2004
Hello
I have come up with this, which looks like a dual-edge FF but with some
limitations: it is not absolutely synchronous, and it can not handle
signal variations faster than the clock period but it still offers a
half-period resolution:

library ieee;
use ieee.std_logic_1164.all;

entity deff is
port (
d : in std_ulogic;
q : out std_ulogic;
clk : in std_ulogic;
rst : in std_ulogic);
end entity deff;

architecture rtl of deff is
signal qp : std_ulogic;
signal qn : std_ulogic;
signal qi : std_ulogic;
signal ck : std_ulogic;

begin

q <= qi;
ck <= qp xor qn;

process (clk, rst) is
begin -- process
if rst = '1' then
qp <= '0';
elsif rising_edge(clk) then
qp <= d;
end if;
end process;

process (clk, rst) is
begin -- process
if rst = '1' then
qn <= '0';
elsif falling_edge(clk) then
qn <= d;
end if;
end process;

process (rst, ck) is
begin -- process
if rst = '1' then
qi <= '0';
elsif rising_edge(ck) then
qi <= not qi;
end if;
end process;

end architecture rtl;

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 
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Ralf Hildebrandt
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Posts: n/a
 
      10-12-2004
Nicolas Matringe wrote:

> I have come up with this, which looks like a dual-edge FF but with some
> limitations:


Hmmm ... 3 flipflops for dual-edge behavior?
What about

--------------------------------
signal reset,clk,D,ff_rise,ff_fall,de_dff : std_ulogic;

process(reset,clk)
begin
if (reset='1') then
ff_rise<='0';
elsif rising_edge(clk) then
ff_rise<=ff_fall XOR D;
end if;
end process;

process(reset,clk)
begin
if (reset='1') then
ff_fall<='0';
elsif falling_edge(clk) then
ff_fall<=ff_rise XOR D;
end if;
end process;

de_dff<=ff_rise XOR ff_fall;
--------------------------------

I call this thing a "pseudo dual-edge D-flipflop" (de_dff).
In real life one will not use plain D-flipflop behavior, but something like

process(reset,clk)
begin
if (reset='1') then
ff_rise<='0';
elsif rising_edge(clk) then
if (ff_fall='1' AND state=some_state AND some_signal='1') then
ff_rise<=some_other_signal;
else -- and so on...
end if;
end if;
end process;


I used this pseudo dual-edge flipflop for generating a manchester coded
output signal (everytime a transition at the begin of a bit and
additionally a transition in the middle of the bit, if a '0' is
transferred). It was very helpful for a low-power solution.

Ralf
 
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