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Enable/disable operation

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I am currently working on a design in VHDL which contains a few modules. My
question is what must I do in order to have one of the modules enabled
whenever I want. In other words, I want the specified module to start
working after some ns, but before that I want it "dead".

Thank you in advance for your help. )

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Dear Aliki, If I understand your question, You want to have some modules in
your project. You want to build HIRARCH project within which to manage the
work of your modules!? If I'm wrong, just tell me. O'K, however, don't
forget that The all modules can start when accept Their input conditions
and CLK signal. You can use signals which are going to do functions as
"CS"-chip select, or "GE"-group enable.
I am sure that you know how to use system signals which connecting
different modudles. For this reason I won't to explane you that.
Best Regards:
Ivaylo Krumov

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