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Hi,

I am trying to simulate the Example Instance of the Altera DDR SDRAM Controller
IP Core.

As described in the DDR SDRAM MegaCoreFunction User Guide
I type the following command under Modelsim
to simulate the IP functional simulation model.
set use_simgen_model 1
source example_controller_ddr_sdram_vsim.tcl

When running the tcl script I get error messages that several signals
are not found, for example:
# ** Error: No objects found matching "/DDR_SDRAM_top_tb/dut/local_rdata"
# Executing ONERROR command at macro ./wave.do line 35

What is going wrong ?

One additional question:

What is the difference if I simulate the pre-compiled ModelSim VHDL libraries
or if I simulate with an IP functional simulation model (DDR SDRAM MegaCore
Function UserGuide page 43) ?

Maybe someone has tried to get startet with the IP Core and has some
idea of what goes wrong ...

I am using QuartusII v. 4.1 SP1 and Modelsim Altera 5.8.c

Kind regards