Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > How to purposely make pipelining in Handel-C?

Thread Tools

How to purposely make pipelining in Handel-C?

Posts: n/a
Hi, all,

How to purposely make pipelining in Handel-C?

Say, I need to read in a lot of 64-bit numbers using Celoxica's DSM (Data Stream
Manager). Since DsmWord is 32-bit in length, two DsmRead and one assignment are
needed. Can I pipeline these two DsmRead and the assignment statement?
Hopefully, I can just maintain 4 32-bit variables (temp1 to temp4) for DsmRead.
When I concatenate temp1 and temp2 and assign the value to a 64-bit variable v1,
I can read in 2 DsmWords to temp3 and temp4. Then, while do concatenation on
temp3 and temp4 to assign to v2, I can read into temp1 and temp2, and will
concatenate them to v3 in the next clock cycle. To achieve the above, how to
write the handel-C code?

By the way, is there any means to directly assign a 32-bit value read from DSM
to a portion of a 64-bit variable?

Thanks a lot!

Best regards,
Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Found one rag that purposely alters photos RichA Digital Photography 8 02-11-2012 04:28 PM
Does Netflix purposely screw U w/ delays? DVD Video 15 07-21-2006 01:19 PM
enable pipelining on Firefox D Cheung Firefox 1 02-07-2005 12:42 PM
Pipelining in VHDL koko VHDL 2 04-29-2004 06:51 PM
purposely misframed 4:3 tv episodes on dvd Waterperson77 DVD Video 0 02-17-2004 11:53 PM