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Hi!

I'd like to instantiate a component with generic parameters within a
test bench. I would like one of the generic pameters to be defined
within a file. Unfortunately, I can't declare a variable within a
generate statement and I can't declare it as a signal neither. And I
can't instantiate a component within a process statement. Any thoughts
about it can be done? Thanks

On 30 Aug 2004 17:13:14 -0700, (Louis Dupont)
wrote:

>Hi!
>
> I'd like to instantiate a component with generic parameters within a
>test bench. I would like one of the generic pameters to be defined
>within a file. Unfortunately, I can't declare a variable within a
>generate statement and I can't declare it as a signal neither. And I
>can't instantiate a component within a process statement. Any thoughts
>about it can be done? Thanks

The "generic parameters" must be known at elaboration time. This
happens before you can perform file I/O. Therefore this can't be done
directly in VHDL.

There are probably many ways to work around your problem though, one
of which would be using a scripting language to read the file and
write some VHDL (with the generic values read from the file). This
VHDL would then be compiled, elaborated and run (possibly by the same
script).

Regards,
Allan

Louis Dupont wrote:

> Hi!
>
> I'd like to instantiate a component with generic parameters within a
> test bench. I would like one of the generic pameters to be defined
> within a file.

A package body containing deferred constants could be
stored in a file.

Or a script file could supply the constants
via a command line option to the sim or synth program.

-- Mike Treseler