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VHDL - Wait on...

 
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Old 08-26-2004, 05:52 AM   #1
Default Wait on...


Is there something that can be done with a WAIT ON statement that CANNOT
be done using a sensitivity list to a process other than allowing a
dynamic sensitivity (order of Wait statements in process)





VHDL User
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Old 08-26-2004, 06:22 AM   #2
Allan Herriman
 
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Default Re: Wait on...
On Thu, 26 Aug 2004 06:52:12 +0200, VHDL User
<> wrote:

>Is there something that can be done with a WAIT ON statement that CANNOT
>be done using a sensitivity list to a process other than allowing a
>dynamic sensitivity (order of Wait statements in process)


For synthesisable code, no.

In simulation, yes, since you can say:

wait [on {SIGID,}] [until expr] [for time];

e.g.

wait until foo for 1 ns;

which gives you a timeout.

Regards,
Allan.


Allan Herriman
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Old 08-30-2004, 08:36 PM   #3
Edmond Cote
 
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Default Re: Wait on...
Allan Herriman wrote:
> On Thu, 26 Aug 2004 06:52:12 +0200, VHDL User
> <> wrote:
>
>
>>Is there something that can be done with a WAIT ON statement that CANNOT
>>be done using a sensitivity list to a process other than allowing a
>>dynamic sensitivity (order of Wait statements in process)

>
>
> For synthesisable code, no.
>
> In simulation, yes, since you can say:
>
> wait [on {SIGID,}] [until expr] [for time];
>
> e.g.
>
> wait until foo for 1 ns;
>
> which gives you a timeout.
>
> Regards,
> Allan.



How about with behavioural synthesis tools?.. can anyone suggest any
good ones?

Thanks,

Ed


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