generic concatenation

Hey all. What's the best way to perform, if possible, a generic
concatenation?

This is my original code:

PARAMS <= param(0) & param(1) & param(2) & param(3) & param(4);

But I'd like to make it generic to a given number of "param"s. I've
tried something like this:

generic(pnum : integer := 5);

Chad

On 25 Aug 2004 09:30:54 -0700, (Chad) wrote:

>Hey all. What's the best way to perform, if possible, a generic
>concatenation?
>
>This is my original code:
>
> PARAMS <= param(0) & param(1) & param(2) & param(3) & param(4);

Am I right in guessing that "param" is a rather large array of
things, and your generic "pnum" specifies how many of its
entries you need?

>But I'd like to make it generic to a given number of "param"s. I've
>tried something like this:
>
> generic(pnum : integer := 5);
> .
> .
> .
> process(param)
> variable param_var : std_logic_vector(pnum-1 downto 0);
> begin
> for i in 0 to pnum-1 loop
> param_var := param_var & param(i);
> end loop;
> PARAMS <= param_var;
> end process;
>
>Ideally, if I do it properly, it should synthesize to nothing but
>wires since it is just a reordering of wires. Any ideas?

Can't really see what's wrong with what you are doing, although the
iterative concatenation is a little clunky.

If you are sure you want parameters param(0) to param(pnum-1),
why not simply

PARAMS <= param(0 to pnum-1);

??? Copying proceeds in left-to-right order; the subscript
numbers have no effect on the copying process. Of course,
if this is to work, "param" must already have been declared as
std_logic_vector(0 to ...);

Sorry if I've missed something important...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley

Hi Johnathan. Sorry, I wasn't specific enough, so the answer seems
obvious. "param" is actually an array of 8-bit std_logic_vector's:

generic(pnum : integer := 24);

Chad

On 25 Aug 2004 15:33:23 -0700, (Chad) wrote:

>Hi Johnathan. Sorry, I wasn't specific enough, so the answer seems
>obvious. "param" is actually an array of 8-bit std_logic_vector's:
>
> generic(pnum : integer := 24);
> .
> .
> .
> PARAMS : out std_logic_vector(pnum*8-1 downto 0);
> .
> .
> .
> type param_array is array(0 to pnum-1) of std_logic_vector(7 downto
>0);
>
> signal param : param_array;
>
>So, I'm trying to concatenate all the individual "param"s to form
>PARAMS, generically. The ordering of bits in PARAMS is not a problem
>at this point. Any improvements to the clunky code is appreciated.

OK, sorry, now I understand. You have an array of arrays, and you
need to flatten them to a single wide array.

Assuming all the subscripts go in a sensible order (and if they
don't, you can easily fix it with alias or intermediate variables):

process (param)
constant wordsize: positive := 8; -- probably defined elsewhere
constant wordmax : integer := wordsize-1;
begin
for word in param'range loop
PARAMS(wordsize*word + wordmax downto wordsize*word)
<= param(word);
end loop;
end process;

If you need to do this a lot, it might be a good idea to write
an array-flattening function...

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley

Thanks Johnathan, that did it.

Chad

Chad