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#1 |
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Hello.
This might be a very simple question. In VHDL it it possible the use the keyword AFTER for signal assignment. Question: Is this time delay only for simulation or also for the synthesis ? If it is also for synthesis - how is it possible to generate a delay of exactly e.g. 175,3 ps ?? How is it synthesized / How is done in hardware?? Thanks for any helpful explanations Greetings, Tobias Möglich Tobias =?iso-8859-1?Q?M=F6glich?= |
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#2 |
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Posts: n/a
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Tobias Möglich wrote:
> This might be a very simple question. > In VHDL it it possible the use the keyword AFTER for signal assignment. > > Question: > Is this time delay only for simulation or also for the synthesis ? > If it is also for synthesis - how is it possible to generate a delay of > exactly e.g. 175,3 ps ?? > How is it synthesized / How is done in hardware?? Hello Tobias, the AFTER keyword will be ignored by the synthesis. There is no way to synthesize a timing-delay. There are possibilities to synthesize some delays by constraints in the synthesis, but not exact. greetings, Steffen Netz Steffen Netz |
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