DDR SDRAM

Hi,

I have a question concerning the write operation for a DDR SDRAM with
a burst
length of 1:

If you have a look at
http://mitglied.lycos.de/vazquez78
you can see the sequence of eight back-to-back write requests that go
to two different rows in the DDR SDRAM device. In the shown instance
(DDR
SDRAM Controller MegaCore User Guide Altera) the burst length is one
on the Controller Local Interface and two on the Memory Side.

My question:
Why do the addresses on the local interface "local_col_addr"
"020","021","022","023","030","031","032","033 "
turn to the memory addresses
"0040","0042","0044","0046","0060","0062","0064"," 0066" on the DDR
SDRAM Interface ?

It is said later in the User Guide that the controller runs the DQ
port to
the DDR devices at one half the width and twice the rate of the DATAIN
port (input data at the local interface of the controller).

But how are the coherence with the shown example addresses?

Thank you in advance.

Rgds
André

ALuPin

(ALuPin) writes:
> My question:
> Why do the addresses on the local interface "local_col_addr"
> "020","021","022","023","030","031","032","033 "
> turn to the memory addresses
> "0040","0042","0044","0046","0060","0062","0064"," 0066" on the DDR
> SDRAM Interface ?
>
> It is said later in the User Guide that the controller runs the DQ
> port to the DDR devices at one half the width and twice the rate of
> the DATAIN port (input data at the local interface of the
> controller).
>
> But how are the coherence with the shown example addresses?

Because the internal interface has a data width of sixteen bit while
the the SDRAM interface is only eight bits wide...

--Marcus

Marcus Harnisch

Marcus Harnisch <> wrote in message news:<>...
> (ALuPin) writes:
> > My question:
> > Why do the addresses on the local interface "local_col_addr"
> > "020","021","022","023","030","031","032","033 "
> > turn to the memory addresses
> > "0040","0042","0044","0046","0060","0062","0064"," 0066" on the DDR
> > SDRAM Interface ?
> >
> > It is said later in the User Guide that the controller runs the DQ
> > port to the DDR devices at one half the width and twice the rate of
> > the DATAIN port (input data at the local interface of the
> > controller).
> >
> > But how are the coherence with the shown example addresses?
>
> Because the internal interface has a data width of sixteen bit while
> the the SDRAM interface is only eight bits wide...
>
> --Marcus

But if it is 8bit wide why is 020 used and not 20 ?
And what about that DQ port to the DDR device is one half the width ?

Rgds
Andre

ALuPin

Hi Andre,

Don't get me wrong, but if you are trying to decypher the waves at the
SDRAM interface it would help if you'd know about some of the basics
of DDR SDRAMs. The "usual suspects" (Micron, Samsung, etc.) provide
good datasheets for download. JEDEC79x (x >= C) might be a little
dry but is certainly the most comprehensive source of information in
that respect.

Good luck,
Marcus

Marcus Harnisch

Marcus Harnisch <> wrote in message news:<>...
> Hi Andre,
>
> Don't get me wrong, but if you are trying to decypher the waves at the
> SDRAM interface it would help if you'd know about some of the basics
> of DDR SDRAMs. The "usual suspects" (Micron, Samsung, etc.) provide
> good datasheets for download. JEDEC79x (x >= C) might be a little
> dry but is certainly the most comprehensive source of information in
> that respect.
>
> Good luck,
> Marcus

Hi Marcus,

could you tell me where to find that JEDEC79x ?

Thank you

André

ALuPin

Umm, might not be that obvious, but how about checking out
http://www.jedec.org/ ?

-- Marcus

Marcus Harnisch

Marcus Harnisch wrote:
> Hi Andre,
>
> Don't get me wrong, but if you are trying to decypher the waves at the
> SDRAM interface it would help if you'd know about some of the basics
> of DDR SDRAMs. The "usual suspects" (Micron, Samsung, etc.) provide
> good datasheets for download. JEDEC79x (x >= C) might be a little
> dry but is certainly the most comprehensive source of information in
> that respect.
>

I personally find the Micron data sheets to be very good references, myself.

-hpa

H. Peter Anvin