CALL FOR PAPERS, IEEE ISQED'05

Call for Papers

ISQED 2005
6th IEEE International Symposium on

QUALITY ELECTRONIC DESIGN

March 28-30, 2005
San Jose, CA, USA

www.isqed.org

DESIGN FOR QUALITY IN THE ERA OF UNCERTAINTY


ISQED is the pioneer and leading international conference dealing with the
design for manufacturability and quality issues front-to-back.
ISQED spans three days, Monday through Wednesday, in three parallel tracks,
hosting near 100 technical
presentations, six keynote speakers, two-three panel discussions, workshops
/tutorials and other informal meetings.
Conference proceedings are published by IEEE Computer Society and hosted in
the digital library. Proceedings CD ROMs
are published by ACM. In addition, continuing the tradition of reaching a
wider readership in the IC design community,
ISQED will continue to publish special issues in leading journals. The
authors of high quality papers will be invited
to submit an extended version of their papers for the special journal
issues.


IMPORTANT DATES:

Paper Submission Deadline September 30, 2004
Acceptance Notification November 17-19, 2004
Final Camera-Ready Paper December 15, 2004


Papers are requested in the following areas:

o Design for Manufacturability & Quality
o Package - Design Interaction & Co-Design
o Design Verification and Design for Testability
o Embedded Test Methodologies
o Robust Device, Interconnect, and Circuits
o EDA Tools & IP Blocks; Interoperability and Implications
o Physical Design, Methodologies & Tools
o Effect of Technology on IC Design, Performance, Reliability & Yield
o Design Quality Definitions, Metrics, and Standards
o Quality Driven Design Flows; SoC, ASIC, FPGA, RF, Memory, etc.
o Quality of Modeling Abstractions and Methods (Device, Interconnect,
Micro and Macro Cells, IP Blocks, ...)
O System-level Design, Methodologies & Tools
o Redundancy & Self Correction Design Techniques
o Management of Design Process, and Design Database
o Global, Social, and Economic Implications of Design Quality
o Quality based EDA Tools, Design Techniques, and Methodologies, dealing
with issues such as:

Timing Closure
R, L, C Extraction
Ground/Vdd Bounce
Signal Noise/Cross-Talk /Substrate Noise
Voltage Drop, Power Rail Integrity
Metal Migration, Hot Carriers
High Frequency Effects
Thermal Effects
Power Estimation
Plasma Induced Damage, and other yield limiting effects
EMI/EMC
Proximity Correction & Phase Shift Methods
erification (Layout, Circuit, Function, etc.)
EOS/ESD
Packaging Modeling and Simulations


Submission Process

The guidelines for the final paper format is provided on the conference web
site at www.isqed.org.
Authors should submit FULL-LENGTH, original, unpublished papers (Minimum 4,
maximum 6 pages).
To permit a blind review, do not include name(s) or affiliation(s) of the
author(s) on the manuscript and abstract.
Submit your papers using the on-line paper submission procedure available in
the ISQED web site. Please check the as-printed
appearance of your paper before submitting the paper. Address all other
inquiries to .

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