Back Annotation simulations

Hi colleagues,

I have got a SDF file from another colleague. I need to do back-annotated
simulations on this design. Now I would like to know what tools and the
procedure should be followed for doing the back-annotation simulations. This
is the first time for me to do back-annotated simulations.


Thanks in advance.
rajan

rajan

You'll need the gate level .vhd file that goes with the .sdf file.
(I think).
Niv.

"rajan" <> wrote in message
news:cf2f8d$8la$...
> Hi colleagues,
>
> I have got a SDF file from another colleague. I need to do back-annotated
> simulations on this design. Now I would like to know what tools and the
> procedure should be followed for doing the back-annotation simulations.
This
> is the first time for me to do back-annotated simulations.
>
>
> Thanks in advance.
> rajan
>
>

Niv

Hi,

I think you can do time analysis and power analysis in PrimeTime and
Power compiler of Synopsys respectively. Those tools can work on gate
level netlist, usually for architecture design.

In PrimeTime and power compiler, if you don't use SDF file, you can
define a wireload model to estimate the wire parasistics and
resistance. Anyway, the model is not accurate, since it doesn't
consider placement&route. So you need back-annotation.

I think SDF file only talk about the wires (P&R) but gates. Gates
information can be extracted from Synopsys library.

If you already extracted transistor level netlist from layout. You can
run Hspice, Spetre or NanoSim (much faster) for the simulation. In
this case, the back-annotation is not neccessary.

If I am not right, correct me please.


"rajan" <> wrote in message news:<cf2f8d$8la$>...
> Hi colleagues,
>
> I have got a SDF file from another colleague. I need to do back-annotated
> simulations on this design. Now I would like to know what tools and the
> procedure should be followed for doing the back-annotation simulations. This
> is the first time for me to do back-annotated simulations.
>
>
> Thanks in advance.
> rajan

Lee

Hi,

Thanks a lot. In case of doing back-annotation, which tools can be used. Is
this possible with NCsim? Also, is the procedure of doing the
back-annotation same as normal functional simulations with NCsim?

rajan
"Lee" <> wrote in message
news: om...
> Hi,
>
> I think you can do time analysis and power analysis in PrimeTime and
> Power compiler of Synopsys respectively. Those tools can work on gate
> level netlist, usually for architecture design.
>
> In PrimeTime and power compiler, if you don't use SDF file, you can
> define a wireload model to estimate the wire parasistics and
> resistance. Anyway, the model is not accurate, since it doesn't
> consider placement&route. So you need back-annotation.
>
> I think SDF file only talk about the wires (P&R) but gates. Gates
> information can be extracted from Synopsys library.
>
> If you already extracted transistor level netlist from layout. You can
> run Hspice, Spetre or NanoSim (much faster) for the simulation. In
> this case, the back-annotation is not neccessary.
>
> If I am not right, correct me please.
>
>
> "rajan" <> wrote in message
news:<cf2f8d$8la$>...
> > Hi colleagues,
> >
> > I have got a SDF file from another colleague. I need to do
back-annotated
> > simulations on this design. Now I would like to know what tools and the
> > procedure should be followed for doing the back-annotation simulations.
This
> > is the first time for me to do back-annotated simulations.
> >
> >
> > Thanks in advance.
> > rajan

rajan

Hi,

usually you instantiate the netlist in a testbench, compile the netlist and
the testbench and start the simulator.
You also need the compiled library for the gate primitives.

The sdf file can be overlayed for timing simulations. Check the simulator
docs on how to do that.
For modelsim the invocation command for the simulator may look like this

vsim -sdftyp /tb_netlist/dut=/home/sim/ab/xc_nl/evalTop_timesim.sdf -t ps
work.cfg_tb_netlist

-sdftyp determines which of the timings in the sdf triplet file will be used
(min, typ or max). You may get different sdf files for different operating
conditions.
/tb_netlist/dut is the hierarchy on which the sdf is overlayed
/home//sim/ab/xc_nl/evalTop_timesim.sdf is the the path and the filename of
the sdf file.
work.cfg_tb_netlist is the testbench configuration

HTH

Ansgar
--
Attention please, reply address is invalid, please remove "_xxx_" ro reply

"rajan" <> schrieb im Newsbeitrag
news:cf5jl9$i24$...
> Hi,
>
> Thanks a lot. In case of doing back-annotation, which tools can be used.
Is
> this possible with NCsim? Also, is the procedure of doing the
> back-annotation same as normal functional simulations with NCsim?
>
> rajan
> "Lee" <> wrote in message
> news: om...
> > Hi,
> >
> > I think you can do time analysis and power analysis in PrimeTime and
> > Power compiler of Synopsys respectively. Those tools can work on gate
> > level netlist, usually for architecture design.
> >
> > In PrimeTime and power compiler, if you don't use SDF file, you can
> > define a wireload model to estimate the wire parasistics and
> > resistance. Anyway, the model is not accurate, since it doesn't
> > consider placement&route. So you need back-annotation.
> >
> > I think SDF file only talk about the wires (P&R) but gates. Gates
> > information can be extracted from Synopsys library.
> >
> > If you already extracted transistor level netlist from layout. You can
> > run Hspice, Spetre or NanoSim (much faster) for the simulation. In
> > this case, the back-annotation is not neccessary.
> >
> > If I am not right, correct me please.
> >
> >
> > "rajan" <> wrote in message
> news:<cf2f8d$8la$>...
> > > Hi colleagues,
> > >
> > > I have got a SDF file from another colleague. I need to do
> back-annotated
> > > simulations on this design. Now I would like to know what tools and
the
> > > procedure should be followed for doing the back-annotation
simulations.
> This
> > > is the first time for me to do back-annotated simulations.
> > >
> > >
> > > Thanks in advance.
> > > rajan
>
>

Ansgar Bambynek