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08-06-2004, 10:29 AM
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#1 |
USB vhdl code (followup)
Since no followups of elder messages seems to be possible, I started
this as new message. Opencores.org provides a USB 1.1 IP in verilog. Not in VHDL. A student of my university has created a USB 1.1 IP in VHDL. Rob Rob Maris |
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08-06-2004, 06:14 PM
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#2 |
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Posts: n/a
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Re: USB vhdl code (followup)
> A student of my university has created a USB 1.1 IP in VHDL.
Possible to get this code ? Regards, Martin Martin Maurer |
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08-07-2004, 12:40 AM
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#3 |
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Re: USB vhdl code (followup)
I would like to see the code too...
Thanks, Don "Martin Maurer" <> wrote in message news:cf0e8t$3jj$04$... > > A student of my university has created a USB 1.1 IP in VHDL. > > Possible to get this code ? > > Regards, > > Martin > > Don Golding |
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08-08-2004, 11:10 AM
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#4 |
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Posts: n/a
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Re: USB vhdl code (followup)
"Rob Maris" <> wrote in message news: om... > Since no followups of elder messages seems to be possible, I started > this as new message. > > Opencores.org provides a USB 1.1 IP in verilog. Not in VHDL. > > A student of my university has created a USB 1.1 IP in VHDL. > > Rob Are you guys going to add it to opencores.org ? Alex Gibson |
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