Port map with combining

Hi,

I have a component that wants a std_logic_vector of 4 bits.
Now, I have a std_logic and a std_logic_vector of 3 bits.

Is it possible to port map it without defining an intermediate signal, like

signal vect : std_logic_vector(2 downto 0);
signal bit : std_logic;

.... port map (
vect4bit => bit & vect,
...
);

But that doesn't work ...



Sylvain Munaut

Sylvain Munaut

Sylvain,
Assuming that vect4bit has the range 3 downto 0:

port map (
vect4bit(3) => bit,
vect4bit(2 downto 0) => vect,
. . .
) ;

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
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Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

> Hi,
>
> I have a component that wants a std_logic_vector of 4 bits.
> Now, I have a std_logic and a std_logic_vector of 3 bits.
>
> Is it possible to port map it without defining an intermediate signal, like
>
> signal vect : std_logic_vector(2 downto 0);
> signal bit : std_logic;
>
> ... port map (
> vect4bit => bit & vect,
> ...
> );
>
> But that doesn't work ...
>
>
>
> Sylvain Munaut

Jim Lewis

Jim Lewis wrote:
> Sylvain,
> Assuming that vect4bit has the range 3 downto 0:
>
> port map (
> vect4bit(3) => bit,
> vect4bit(2 downto 0) => vect,
> . . .
> ) ;
>
> Cheers,
> Jim

Exactly thanks !

I havent't seen such an example in tutorials/intro, pity ;(


Sylvain

Sylvain Munaut