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VHDL - tri-state buffer with Xilinx ECS |
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08-02-2004, 04:56 PM
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#1 |
tri-state buffer with Xilinx ECS
i am using Xilinx ECS to implement an i2c interface.
i ve got an input sda_i and an output sda_o . it s working well but i now would like to use an input/output SDA. I tried to use the symbol "iobuf" with: IO=SDA with a pull-up T=sda_o with an inverser I=pull down O=sda_i Simulation shows that '0' is ok, '1' goes like 'X' ... thanks for help Mai |
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08-10-2004, 12:02 AM
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#2 |
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Posts: n/a
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Re: tri-state buffer with Xilinx ECS
"Mai" <mai@hide> wrote in message news:< alkaboutprogramming.com>...
> i am using Xilinx ECS to implement an i2c interface. > i ve got an input sda_i and an output sda_o . > it s working well but i now would like to use an input/output SDA. I tried > to use the symbol "iobuf" with: > > IO=SDA with a pull-up > T=sda_o with an inverser > I=pull down > O=sda_i > > Simulation shows that '0' is ok, '1' goes like 'X' ... > > thanks for help Remove I=pull down. The reason X is there are two signals driving the line at the same time, causing data uncertainty. Weng Weng Tianxiang |
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