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Hi,
I have a schematic where N components output each one a reset signal,
which is given in input to one other component. The line connecting
the resets is something like:

reset <= res_1 or res_2 or res_3 or ... or res_N;

This synthetize fine, but modelsim gives me the following error on the
line above:

Error: router_test_arch.vhd(709): Delay in signal assignment must be
ascending.

Can somebody tell me what to look for? I've no clue.....


RA

I have the feeling that the error message has nothing to do with the line
you show.
This error message occurs when you assign to a signal something like:

y <= '0' after 10 ns,
'1' after 5 ns; -- time not ascending;

Correct is
y <= '1' after 5 ns,
'0' after 10 ns;

Egbert Molenkamp

"ra" <> wrote in message news:LJDOc.54619$8_6.54083@attbi_s04...
> Hi,
> I have a schematic where N components output each one a reset signal,
> which is given in input to one other component. The line connecting
> the resets is something like:
>
> reset <= res_1 or res_2 or res_3 or ... or res_N;
>
> This synthetize fine, but modelsim gives me the following error on the
> line above:
>
> Error: router_test_arch.vhd(709): Delay in signal assignment must be
> ascending.
>
> Can somebody tell me what to look for? I've no clue.....
>
>
> RA

I would have understood that, but I'm not using explicitly any "after"
or "wait". Also, replacing the line I mentioned with just

reset <= res_1

solves the problem.



Egbert Molenkamp wrote:
> I have the feeling that the error message has nothing to do with the line
> you show.
> This error message occurs when you assign to a signal something like:
>
> y <= '0' after 10 ns,
> '1' after 5 ns; -- time not ascending;
>
> Correct is
> y <= '1' after 5 ns,
> '0' after 10 ns;
>
> Egbert Molenkamp
>
> "ra" <> wrote in message news:LJDOc.54619$8_6.54083@attbi_s04...
>
>>Hi,
>>I have a schematic where N components output each one a reset signal,
>>which is given in input to one other component. The line connecting
>>the resets is something like:
>>
>>reset <= res_1 or res_2 or res_3 or ... or res_N;
>>
>>This synthetize fine, but modelsim gives me the following error on the
>>line above:
>>
>>Error: router_test_arch.vhd(709): Delay in signal assignment must be
>>ascending.
>>
>>Can somebody tell me what to look for? I've no clue.....
>>
>>
>> RA
>
>
>

Strange ..

Maybe you can remove (comment) parts of the description to find out when it
is wrong/right. You already did it with the or chain for the reset. Maybe
fine tuning can find the problem.
You may also send me the VHDL description. Maybe I see what the problem is.

Egbert Molenkamp

"ra" <> wrote in message news:...
> I would have understood that, but I'm not using explicitly any "after"
> or "wait". Also, replacing the line I mentioned with just
>
> reset <= res_1
>
> solves the problem.
>
>
>
> Egbert Molenkamp wrote:
> > I have the feeling that the error message has nothing to do with the
line
> > you show.
> > This error message occurs when you assign to a signal something like:
> >
> > y <= '0' after 10 ns,
> > '1' after 5 ns; -- time not ascending;
> >
> > Correct is
> > y <= '1' after 5 ns,
> > '0' after 10 ns;
> >
> > Egbert Molenkamp
> >
> > "ra" <> wrote in message
news:LJDOc.54619$8_6.54083@attbi_s04...
> >
> >>Hi,
> >>I have a schematic where N components output each one a reset signal,
> >>which is given in input to one other component. The line connecting
> >>the resets is something like:
> >>
> >>reset <= res_1 or res_2 or res_3 or ... or res_N;
> >>
> >>This synthetize fine, but modelsim gives me the following error on the
> >>line above:
> >>
> >>Error: router_test_arch.vhd(709): Delay in signal assignment must be
> >>ascending.
> >>
> >>Can somebody tell me what to look for? I've no clue.....
> >>
> >>
> >> RA
> >
> >
> >