Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > help with modelsim error (delay in signal assignment must be ascending)

Reply
Thread Tools

help with modelsim error (delay in signal assignment must be ascending)

 
 
ra
Guest
Posts: n/a
 
      07-31-2004
Hi,
I have a schematic where N components output each one a reset signal,
which is given in input to one other component. The line connecting
the resets is something like:

reset <= res_1 or res_2 or res_3 or ... or res_N;

This synthetize fine, but modelsim gives me the following error on the
line above:

Error: router_test_arch.vhd(709): Delay in signal assignment must be
ascending.

Can somebody tell me what to look for? I've no clue.....


RA
 
Reply With Quote
 
 
 
 
Egbert Molenkamp
Guest
Posts: n/a
 
      08-03-2004
I have the feeling that the error message has nothing to do with the line
you show.
This error message occurs when you assign to a signal something like:

y <= '0' after 10 ns,
'1' after 5 ns; -- time not ascending;

Correct is
y <= '1' after 5 ns,
'0' after 10 ns;

Egbert Molenkamp

"ra" <(E-Mail Removed)> wrote in message news:LJDOc.54619$8_6.54083@attbi_s04...
> Hi,
> I have a schematic where N components output each one a reset signal,
> which is given in input to one other component. The line connecting
> the resets is something like:
>
> reset <= res_1 or res_2 or res_3 or ... or res_N;
>
> This synthetize fine, but modelsim gives me the following error on the
> line above:
>
> Error: router_test_arch.vhd(709): Delay in signal assignment must be
> ascending.
>
> Can somebody tell me what to look for? I've no clue.....
>
>
> RA



 
Reply With Quote
 
 
 
 
ra
Guest
Posts: n/a
 
      08-03-2004
I would have understood that, but I'm not using explicitly any "after"
or "wait". Also, replacing the line I mentioned with just

reset <= res_1

solves the problem.



Egbert Molenkamp wrote:
> I have the feeling that the error message has nothing to do with the line
> you show.
> This error message occurs when you assign to a signal something like:
>
> y <= '0' after 10 ns,
> '1' after 5 ns; -- time not ascending;
>
> Correct is
> y <= '1' after 5 ns,
> '0' after 10 ns;
>
> Egbert Molenkamp
>
> "ra" <(E-Mail Removed)> wrote in message news:LJDOc.54619$8_6.54083@attbi_s04...
>
>>Hi,
>>I have a schematic where N components output each one a reset signal,
>>which is given in input to one other component. The line connecting
>>the resets is something like:
>>
>>reset <= res_1 or res_2 or res_3 or ... or res_N;
>>
>>This synthetize fine, but modelsim gives me the following error on the
>>line above:
>>
>>Error: router_test_arch.vhd(709): Delay in signal assignment must be
>>ascending.
>>
>>Can somebody tell me what to look for? I've no clue.....
>>
>>
>> RA

>
>
>

 
Reply With Quote
 
Egbert Molenkamp
Guest
Posts: n/a
 
      08-04-2004
Strange ..

Maybe you can remove (comment) parts of the description to find out when it
is wrong/right. You already did it with the or chain for the reset. Maybe
fine tuning can find the problem.
You may also send me the VHDL description. Maybe I see what the problem is.

Egbert Molenkamp

"ra" <(E-Mail Removed)> wrote in message news:(E-Mail Removed)...
> I would have understood that, but I'm not using explicitly any "after"
> or "wait". Also, replacing the line I mentioned with just
>
> reset <= res_1
>
> solves the problem.
>
>
>
> Egbert Molenkamp wrote:
> > I have the feeling that the error message has nothing to do with the

line
> > you show.
> > This error message occurs when you assign to a signal something like:
> >
> > y <= '0' after 10 ns,
> > '1' after 5 ns; -- time not ascending;
> >
> > Correct is
> > y <= '1' after 5 ns,
> > '0' after 10 ns;
> >
> > Egbert Molenkamp
> >
> > "ra" <(E-Mail Removed)> wrote in message

news:LJDOc.54619$8_6.54083@attbi_s04...
> >
> >>Hi,
> >>I have a schematic where N components output each one a reset signal,
> >>which is given in input to one other component. The line connecting
> >>the resets is something like:
> >>
> >>reset <= res_1 or res_2 or res_3 or ... or res_N;
> >>
> >>This synthetize fine, but modelsim gives me the following error on the
> >>line above:
> >>
> >>Error: router_test_arch.vhd(709): Delay in signal assignment must be
> >>ascending.
> >>
> >>Can somebody tell me what to look for? I've no clue.....
> >>
> >>
> >> RA

> >
> >
> >



 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Assignment to output signal from internal signal not istantaneous dibacco73 VHDL 1 02-12-2009 11:28 PM
Problem with assignment Schedule in Modelsim? Tricky VHDL 2 08-13-2007 08:28 AM
Concurrent assignment Modelsim problem. Please, need help ASAP. jason12 VHDL 0 07-29-2007 10:40 AM
"Target of signal assignment is not a signal" Nicolas Moreau VHDL 9 07-25-2007 04:21 PM
Unknown signal resolution in NCsim and Modelsim vrangan@qualcomm.com VHDL 3 12-17-2003 07:07 PM



Advertisments