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Max Min

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i have a vhdl algorithm for compute the min and max of a signal, but
it is not synthesizable.

i have two loops with a IF..THEN statement inside

is it possible to have a if inside a loop ?


-- Tri de la RAM matched du plus petit au plus grand signal
TRI_RAM : process (clk_smp,reset,etat,match_int,ram_match_pos,ram_ma tch_neg)
variable ram_match_pos_int_I, ram_match_pos_int_J, tampon_int :
variable ram_match_neg_int_I, ram_match_neg_int_J : integer;
if reset='1' then
INIT_MATCH_RAM : for I in 0 to N_match-1 loop
ram_match_pos(I) <= (others=>'0');
ram_match_neg(I) <= (others=>'0');
end loop INIT_MATCH_RAM;
seuil_pos <= 0;
seuil_neg <= 0;
case etat is
when etat_0 =>
if match_int > 0 then
etat_suivant <= etat_1;
etat_suivant <= etat_2;
end if;
when etat_1 =>
ram_match_pos(0) <= conv_std_logic_vector(match_int,22);
TRI_MATCH_RAM_POS : for I in 0 to N_match-1 loop
TRI_J_POS : for J in 0 to N_match-1 loop
ram_match_pos_int_I := conv_integer(ram_match_pos(I));
ram_match_pos_int_J := conv_integer(ram_match_pos(J));
tampon_int := ram_match_pos_int_J;
ram_match_pos_int_J := ram_match_pos_int_I;
ram_match_pos_int_I := tampon_int;
if ram_match_pos_int_I > ram_match_pos_int_J then
ram_match_pos(I) <=
ram_match_pos(J) <=
etat_suivant <= etat_1;
ram_match_pos(J) <= ram_match_pos(J);
ram_match_pos(I) <= ram_match_pos(I);
etat_suivant <= etat_1;
end if;
end loop TRI_J_POS;
seuil_pos <= (conv_integer(ram_match_pos(N_match-1))-conv_integer(ram_match_pos(0)))/2;
seuil_neg <= seuil_neg;
etat_suivant <= etat_0;
when etat_2 =>
ram_match_neg(0) <= conv_std_logic_vector(match_int,22);
TRI_MATCH_RAM_MAX_NEG : for I in 0 to N_match-1 loop
TRI_J_MAX_NEG : for J in 0 to N_match-1 loop
ram_match_neg_int_I := conv_integer(ram_match_neg(I));
ram_match_neg_int_J := conv_integer(ram_match_neg(J));
tampon_int := ram_match_neg_int_J;
ram_match_neg_int_J := ram_match_neg_int_I;
ram_match_neg_int_I := tampon_int;
if ram_match_neg_int_I > ram_match_neg_int_J then
ram_match_neg(I) <=
ram_match_neg(J) <=
etat_suivant <= etat_2;
ram_match_neg(J) <= ram_match_neg(J);
ram_match_neg(I) <= ram_match_neg(I);
etat_suivant <= etat_2;
end if;
end loop TRI_J_MAX_NEG;
seuil_neg <= (conv_integer(ram_match_neg(N_match-1))-conv_integer(ram_match_neg(0)))/2;
seuil_pos <= seuil_pos;
etat_suivant <= etat_0;
when others =>
etat_suivant <= etat_0;
end case;
end if;
end process TRI_RAM;

Controle_etat: process(reset,clk_smp)
if reset='1' then
etat <= etat_0;
elsif clk_smp'event and clk_smp='1' then
etat <= etat_suivant;
end if;
end process Controle_etat;
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Jonathan Bromley
Posts: n/a
On 29 Jul 2004 03:18:09 -0700, Removed) (Patrick)

> i have a vhdl algorithm for compute the min and max of a signal, but
> it is not synthesizable.

This is not surprising. You are trying to bubble-sort the whole
contents of a RAM in only one clock cycle.

> i have two loops with a IF..THEN statement inside
> is it possible to have a if inside a loop ?

Yes. The problem is that your next-state logic makes multiple
assignments to various different locations in the memories, all
at the same moment of simulation time.

Try to decide what should happen on each clock cycle. A simple
state machine with only three states will not solve your problem.
Jonathan Bromley, Consultant

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