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Re: I hate VHDL!!!

 
 
Tom Verbeure
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      07-28-2004

> Now take the example and imagine the same case but with a typo error

on
> clk name, which is an other existing signal of the design.
> If the sensitivity list is (*), I have no way to flag the typo error.


> And possibly no tests fail, except perhaps in very hard to find

corner
> case (if both signal have similar behavior, except under very

specific
> cases).


Basically you're saying that you want to (ab?)use the sensititivity
list as a redundancy mechanism against ordinary typos.

At what point do you have to stop holding the hand of a designer and
trust that he will fix typos, run simulations to verify a design and
read the error reports of his synthesis and/or linting tool?

Say a designer writes:
a <= b;
instead of:
a <= c;
How can we protect a designer against such a potentially disastrous
typo?

Tom

 
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Just an Illusion
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Posts: n/a
 
      07-29-2004
Hi,

I have change the subject line, because I think it is no more link with
initial message.

Tom Verbeure wrote:

>>Now take the example and imagine the same case but with a typo error
>>
>>

>on
>
>
>>clk name, which is an other existing signal of the design.
>>If the sensitivity list is (*), I have no way to flag the typo error.
>>
>>

>
>
>
>>And possibly no tests fail, except perhaps in very hard to find
>>
>>

>corner
>
>
>>case (if both signal have similar behavior, except under very
>>
>>

>specific
>
>
>>cases).
>>
>>

>
>Basically you're saying that you want to (ab?)use the sensititivity
>list as a redundancy mechanism against ordinary typos.
>
>

Not exactly, the aspect that you put into the sensitivity list are the
control part of a process.
You can have some mechanism that use content of sensitivity list to make
some check, or some assertion.

When you introduce a new element, you need extend the feature of the
language. In that case I think that is a reduction, because you can't no
more use the sensitivity list.
To me, have no sensitivity list or have (*) in sensitivity list are
equivalent.

>At what point do you have to stop holding the hand of a designer and
>trust that he will fix typos, run simulations to verify a design and
>read the error reports of his synthesis and/or linting tool?
>
>Say a designer writes:
>a <= b;
>instead of:
>a <= c;
>How can we protect a designer against such a potentially disastrous
>typo?
>
>

In that case, that is not a real typo problem, but more a logic problem.
In my example, the typo error is in the sensitivity list content.

To check your case, formal verification, simulation...

>Tom
>
>
>

JaI

 
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Weng Tianxiang
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      07-29-2004
Jim,
I fully agree with Tom's ideas:
1. Never put into consideration any typos for new keywords, new ideas,
new proposals.
2. If you can recognize 3 different types of process(), software can
recognize it much faster and better than you do.

Weng
 
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Wallclimber
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Posts: n/a
 
      07-29-2004
> Not exactly, the aspect that you put into the sensitivity list are the
> control part of a process.
> You can have some mechanism that use content of sensitivity list to make
> some check, or some assertion.
>
> When you introduce a new element, you need extend the feature of the
> language. In that case I think that is a reduction, because you can't no
> more use the sensitivity list.
> To me, have no sensitivity list or have (*) in sensitivity list are
> equivalent.


???

Where did I claim that I wanted to get rid of sensitivity lists? The
(*) notation would be an addition for those cases where it is useful
(like combinational processes...). This is no different than for
Verilog.

Tom
 
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