Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > programming to simulatin

Reply
Thread Tools

programming to simulatin

 
 
fskalka
Guest
Posts: n/a
 
      07-08-2004
We have some programming files (we have rights to the source, and have
hardcopy of the source in schematics, no softcopy) for some ACTEL
FPGAs (AT1240XL and AT1225XL). We are in the process of creating VHDL
code for these parts so we can make changes and do some integration.
We would like to do some simulation to verify our new code against the
old design before we put our new code in hardware.
Does anybody know of a way to create a black box simulation model
(preferably VHDL) for the FPGAs from the programming file? I realize
that a net list is not usable, but the should be able to extract the
input to output logic and timing based on fuse map information.
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
C (functional programming) VS C++ (object oriented programming) Joe Mayo C Programming 168 10-22-2007 01:00 AM
Can Your Programming Language Do This? Joel on functional programming and briefly on anonymous functions! Casey Hawthorne Python 4 08-04-2006 05:23 AM
Wireless PEAP/MSCHAPV2 client programming question Jim Howard Wireless Networking 6 07-02-2005 11:53 AM
systems programming versus application programming Matt Java 35 07-22-2004 08:10 AM
programming to simulatin fskalka VHDL 0 07-08-2004 01:40 PM



Advertisments