Re: mixed Verilog/VHDL design

"botao" <> wrote in message news:<cch877$n40$>...
> Have a tough problem ...
>
> I need to compare 2 components with the same interface, one component is
> implemented in VHDL, the other is in Verilog.
> I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
> the Verilog one into VERILOG_LIB, then I am planning to code up a top level
> testbench in Verilog, something like
>
> comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
> comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB
>
>
> how do I exactly do this in Verilog? I know in VHDL one can do this as
>
> u_vhdl: ENTITY VHDL_LIB.comp ...
>
> but I have to use Verilog this time.
>
> thanks,
>
> ---Lee

I believe that if you use Verilog 2001 configurations, ModelSim
supports referencing components from both Verilog and VHDL libraries.

nemgreen

> I believe that if you use Verilog 2001 configurations, ModelSim
> supports referencing components from both Verilog and VHDL libraries.

As far as you do not use OEM versions of Modelsim ... isn't it?

ALuPin

"ALuPin" <> wrote in message
news: om...
> > I believe that if you use Verilog 2001 configurations, ModelSim
> > supports referencing components from both Verilog and VHDL libraries.
>
> As far as you do not use OEM versions of Modelsim ... isn't it?

I do have the full featured version ... Not using Verilog 2001 yet, can you
guys poing me to any webpage which explains the configuration thing?

---Lee

botao

"botao" <> wrote in message news:ccjs6o$jd8$...
>
> "ALuPin" <> wrote in message
> news: om...
>> > I believe that if you use Verilog 2001 configurations, ModelSim
>> > supports referencing components from both Verilog and VHDL libraries.
>>
>> As far as you do not use OEM versions of Modelsim ... isn't it?
>
> I do have the full featured version ... Not using Verilog 2001 yet, can you
> guys poing me to any webpage which explains the configuration thing?
>

You should not need to use configurations to get this simulated.
Configurations in Verilog are extremely confusing.

If the vhdl entity is compiled (with vcom) in the same library as you compile your verilog design (with vlog),
then I believe that it does get picked up by name by ModelSim.

Another way to go is to write the top level module in VHDL.
There you can use a component configuration to link the instance to the Verilog module.

Or just compile everything in one library, and then there is certainly no dual-language linking problem.

Rob

> ---Lee
>
>
>

Rob Dekker