Hi Salvatore,
I have not try but perhaps with
a <= b(3)(31 downto 0);
JaI
Salvatore Callea wrote:
>I've defined:
>
> type std_logic_matrix is array (natural range <>, natural range <>) of
>std_logic;
>
>
>and:
>
> signal a : std_logic_vector(31 downto 0);
> signal b : std_logic_matrix(1 to 10, 31 downto 0);
>
>
>Why Modelsim report an error during compilation if I assign:
>
> a <= b(3, 31 downto 0);
>
>Is it posible to assign a std_logic_vector with a slice of a
>std_logic_matrix in a more compact way than this:
>
> a(0) <= b(3, 0);
> a(1) <= b(3, 1);
> ...
> a(31) <= b(3, 31);
>
>
>thanks in advance: Salvatore
>
>
