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I'm not completely clear on how to use bidirectional ports in VHDL for
use with connecting to SDRAM shared data lines. How do I specify this
in my state machine if I am to read and then write to the line?

An example:

TX_RX_BUS :INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
....

CASE state IS

WHEN READ =>
TX_RX_BUS (31 DOWNTO 0) <= TX_RX_BUS (31 DOWNTO 0);

WHEN WRITE =>
TX_RX_BUS (31 DOWNTO 0) <= TX_RX_BUS (31 DOWNTO 0);
.....etc..

This is what I wrote in my code, but I am unclear what this actually
means. I know this is incorrect. What I want is somehow to place the
data content on the TX_RX_BUS line connected to my SDRAM, and then
when the SDRAM is in the READ state I can capture the contents of the
same bus as an input line.

Can anyone help me understand whether this is valid, and what the best
way to handle a shared bus for memory?


Regards,
Pino

Pino wrote:

> I'm not completely clear on how to use bidirectional ports in VHDL for
> use with connecting to SDRAM shared data lines. How do I specify this
> in my state machine if I am to read and then write to the line?

http://groups.google.com/groups?q=vhdl+inout+oe

-- Mike Treseler

Mike Treseler <> wrote in message news:<FOqdnUlazdu0K3ndRVn->...
> Pino wrote:
>
> > I'm not completely clear on how to use bidirectional ports in VHDL for
> > use with connecting to SDRAM shared data lines. How do I specify this
> > in my state machine if I am to read and then write to the line?
>
> http://groups.google.com/groups?q=vhdl+inout+oe
>
> -- Mike Treseler

Thanks, I think this might be what I was looking for; however, just
one more clarification in case I mis-interpreted the solution. It
seems from this example you need to identify an input port, an output
port, and the bidirectional port.

When you want to be able to place data to the memory shared data line,
you take this from a instantiated input port and multiplex it directly
to the INOUT bidirectional port using an OE line; i.e, Z <= A;

If you want information from the memory data line, then you multiplex
in the data when OE = '0', and assign it to the bidirectional port,
but to what? This is where I am a bit confused.....sorry. That is Y
<= Z? Is this correct way of interpreting the response

Note Z represents the bidirectional port, A is an input port and Y is
an output port as per the example.

Your help is appreciated....
Pino

Hi Pino,

You must have something like:

Z : inout std_logic;
....

signal A, OE, Y : std_logic;


Z <= A when OE = '1' else '-';
Y <= Z ;

....

That would said that Y always follow the value of Z (and A when OE='1'),
and Z follow value of A only when OE = '1' (Z is output), in any other
case Z is input

JaI

Pino wrote:

>Mike Treseler <> wrote in message news:<FOqdnUlazdu0K3ndRVn->...
>
>
>>Pino wrote:
>>
>>
>>
>>>I'm not completely clear on how to use bidirectional ports in VHDL for
>>>use with connecting to SDRAM shared data lines. How do I specify this
>>>in my state machine if I am to read and then write to the line?
>>>
>>>
>>http://groups.google.com/groups?q=vhdl+inout+oe
>>
>> -- Mike Treseler
>>
>>
>
>Thanks, I think this might be what I was looking for; however, just
>one more clarification in case I mis-interpreted the solution. It
>seems from this example you need to identify an input port, an output
>port, and the bidirectional port.
>
>When you want to be able to place data to the memory shared data line,
>you take this from a instantiated input port and multiplex it directly
>to the INOUT bidirectional port using an OE line; i.e, Z <= A;
>
>If you want information from the memory data line, then you multiplex
>in the data when OE = '0', and assign it to the bidirectional port,
>but to what? This is where I am a bit confused.....sorry. That is Y
><= Z? Is this correct way of interpreting the response
>
>Note Z represents the bidirectional port, A is an input port and Y is
>an output port as per the example.
>
>Your help is appreciated....
>Pino
>
>

Just an Illusion a écrit:
> Hi Pino,
>
> You must have something like:
>
> Z : inout std_logic;
> ...
>
> signal A, OE, Y : std_logic;
>
>
> Z <= A when OE = '1' else '-';
> Y <= Z ;

Canonical form here is
Z <= A when OE = '1' else 'Z';

or, for vectors:
Z <= A when OE = '1' else (others => 'Z');

'-' is "don't care" (never understood what this stands for, actually),
not "high impedance".

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

Nicolas,
> '-' is "don't care" (never understood what this stands for, actually),

By differentiating '-' and 'X', it is possible to
do something reasonable for:
Y <= std_match(A, "10---100") ; -- see numeric_std

case1: If A is 10111100 then Y is true.
case2: If A is XXXXXXXX then Y is false.

If there were only 'X' and no '-', then case 2 would
be true. This would be bad. I believe that this is
one if the issues with Verilog's casex.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Nicolas Matringe <> wrote in message news:<>...
> Just an Illusion a écrit:
> > Hi Pino,
> >
> > You must have something like:
> >
> > Z : inout std_logic;
> > ...
> >
> > signal A, OE, Y : std_logic;
> >
> >
> > Z <= A when OE = '1' else '-';
> > Y <= Z ;
>
> Canonical form here is
> Z <= A when OE = '1' else 'Z';
>
> or, for vectors:
> Z <= A when OE = '1' else (others => 'Z');
>
> '-' is "don't care" (never understood what this stands for, actually),
> not "high impedance".

Thanks this helps clarify the notational details I was trying to think
about. Although from the above example it definitely seems that the
correct way to do this is defining other input & output ports so that
you can tie the shared data bus onto something that can be used to
observe the data (i.e. the Y signal) when it is READ from the memory
and a data line that is required to place data (i.e A) for a WRITE on
the data bus. I had assumed that there was another way to do this.

Also just a point of additional confusing concerning OE. Is the OE
enable line absolutely required, or if in certain portions of my state
machine if I absolutely know that I'm going to READ and WRITE (ie I'm
in that logical state), can I just ignore the inclusion of this
additional input signal and place the data on the line and/or read the
data from the line and store it directly into Y or take the data
directly from A? However, I run into an issue in that I'm not sure
how to invoke my FSM at the higher level to place the data on the bus
line as in the above code, it's keeping things in tristate all the
time. It seems in this instance, that is what I can use the OE line
for.....can someone please help clarify this confusion.

Your help has been excellent thus far...!

Regards
Pino

Pino a écrit:
[...]
>
> Thanks this helps clarify the notational details I was trying to think
> about. Although from the above example it definitely seems that the
> correct way to do this is defining other input & output ports so that
> you can tie the shared data bus onto something that can be used to
> observe the data (i.e. the Y signal) when it is READ from the memory
> and a data line that is required to place data (i.e A) for a WRITE on
> the data bus. I had assumed that there was another way to do this.

What I wrote (and I think most VHDL writers do too ) is a description
of how it is actually done in hardware: you have an output buffer with a
tristate control input, and an input buffer:

_____ OE
|
|/|
___/ |___ A
| \ |
| \|
Z --|
| |\
|___| \___ Y
| /
|/


> Also just a point of additional confusing concerning OE. Is the OE
> enable line absolutely required, or if in certain portions of my state
> machine if I absolutely know that I'm going to READ and WRITE (ie I'm
> in that logical state), can I just ignore the inclusion of this
> additional input signal and place the data on the line and/or read the
> data from the line and store it directly into Y or take the data
> directly from A?

Y will always take data from Z. Always assign a value to A. Enable the
output (i.e. assert OE) only when you really output data.
The two lines I wrote must be placed only in the top-level VHDL file
(well not really "must" but it's more adviseable)


--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/