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Can someone suggest how I can set flags in a combinatorial part of a
Mealy type state machine, that are used to determine how the state
machine vectors between states, without having to clear the flags on
each iteration of the state machine process?

For example, I have states a,b,c,d,e,f. On start-up, the state machine
vectors a->b->c->, in state 'c' some input condition causes the state
machine to vector back to state 'a', with this branch of the state
machine taken, a flag has been set so that when the state machine
vectors 'a' to state 'b' with the flag set, the state machine will
vector from state b to state 'f'. In state 'f' I clear the flag. State
'c' is the only state that the flag is set, state 'f' is the only
state that the flag is cleared.

When I synthesise the state machine, I get a warning
"'flag' is not always assigned. Storage may be needed.."
Am I avoiding generating a latch if I am certain that the flag will be
cleared in a subsequent state, or is this bad practice in general??

Thanks in advance

Sion

Gunit wrote:

> When I synthesise the state machine, I get a warning
> "'flag' is not always assigned. Storage may be needed.."
> Am I avoiding generating a latch if I am certain that the flag will be
> cleared in a subsequent state, or is this bad practice in general??

post your code.
consider simulation before synthesis.
http://groups.google.com/groups?q=state_example

-- Mike Treseler

Hi Sion,

Gunit wrote:

><snip>
>
>When I synthesise the state machine, I get a warning
>"'flag' is not always assigned. Storage may be needed.."
>Am I avoiding generating a latch if I am certain that the flag will be
>cleared in a subsequent state, or is this bad practice in general??
>
>
I don't know how you can avoid to have a flip-flop, because in your
example you have a logic which must maintain a value between two events
(a set event and a clear event).

You can try to define the flag value at each state with:

if (flag = '0') then
flag='0';
else
flag='1';
end if;

but I am not sure that you remove the ff after synthesis by this way.

Question: I am not sure to well understand your example, could you
confirm me if the following pseudo code is the expected once ?

if (reset = '0') then
state <= idle; -- aka a
then (clk'event and clk='1') then
state <= nxt_state;
end if;

case state
when a =>
if (flag = '0') then
nxt_state <= b;
else
nxt_state <= f;
end if;
-- The fsm stays in state a only during one clock cycle
end case;

That's correct ?

JaI