Jim,

Here you are. The longest 'if..elsif..end' statement.

Following the process(), there are two versions of compilation

information for Xilinx chip xc2v1000-4, 1 million gate chip: one for

non-optimized version as follows, another for manually optimized

version that I have been using. Other parts are entirely same.

Their stark differences are:

Minimum period: 14.904ns - 14.687ns = 0.217ns

Number of occupied Slices: 3,432 - 3,369 = 63

Total Number 4 input LUTs: 5,688 - 5,581 = 107

From above observation, we conclude: 'if..elsif..end' is very code

inefficient!!! This is only one counter. If more, you cannot expect to

get what you want for a complex design.

This is the basic reason I want to introduce new keyword 'orif'.

Weng

The process is a counter, it has 7 loading conditions which are

mutually exclusive.

RowChipPtrA : process(nRESETGlobal, CLK66M)

begin

if(nRESETGlobal = '0') then

RowChipPtr <= (others=>'0');

elsif(CLK66M'event and CLK66M = '1') then

if(WriteFIFO_SDRAMPtr) then -- 1

if(MEMORY_2G = '0') then

RowChipPtr(14 downto 0) <= WriteFIFODataOut(29 downto 15);

else

RowChipPtr(14 downto 0) <= WriteFIFODataOut(30 downto 16);

end if;

elsif(AD_R0_SDRAMPtr) then -- 2

if(MEMORY_2G = '0' and WINDOW_16M = '1') then

RowChipPtr(14 downto 0) <= TWindowAddress(29 downto 24) &

AD_R0(23 downto 15);

elsif(MEMORY_2G = '0' and WINDOW_256M = '1') then

RowChipPtr(14 downto 0) <= TWindowAddress(29 downto 2

&

AD_R0(27 downto 15);

elsif(MEMORY_2G = '1' and WINDOW_16M = '1') then

RowChipPtr(14 downto 0) <= TWindowAddress(30 downto 24) &

AD_R0(23 downto 16);

elsif(MEMORY_2G = '1' and WINDOW_256M = '1') then

RowChipPtr(14 downto 0) <= TWindowAddress(30 downto 2

&

AD_R0(27 downto 16);

elsif(MEMORY_2G = '1' and WINDOW_NO = '1') then

RowChipPtr(14 downto 0) <= AD_R0(30 downto 16);

elsif(MEMORY_1G = '1' and WINDOW_NO = '1') then

RowChipPtr(14 downto 0) <= AD_R0(29 downto 15);

elsif(MEMORY_512M = '1' and WINDOW_NO = '1') then

RowChipPtr(14 downto 0) <= '0' & AD_R0(28 downto 15);

else -- when MEMORY_256M = '1' and WINDOW_NO = '1'

RowChipPtr(14 downto 0) <= "00" & AD_R0(27 downto 15);

end if;

elsif(AD_R1_SDRAMPtr) then -- 3

if(MEMORY_2G = '0' and WINDOW_16M = '1') then

RowChipPtr(14 downto 0) <= TWindowAddress(29 downto 24) & AD_R1(23

downto 15);

elsif(MEMORY_2G = '0' and WINDOW_256M = '1') then

RowChipPtr(14 downto 0) <= TWindowAddress(29 downto 2

& AD_R1(27

downto 15);

elsif(MEMORY_2G = '1' and WINDOW_16M = '1') then

RowChipPtr(14 downto 0) <= TWindowAddress(30 downto 24) & AD_R1(23

downto 16);

elsif(MEMORY_2G = '1' and WINDOW_256M = '1') then

RowChipPtr(14 downto 0) <= TWindowAddress(30 downto 2

& AD_R1(27

downto 16);

elsif(MEMORY_2G = '1' and WINDOW_NO = '1') then

RowChipPtr(14 downto 0) <= AD_R1(30 downto 16);

elsif(MEMORY_1G = '1' and WINDOW_NO = '1') then

RowChipPtr(14 downto 0) <= AD_R1(29 downto 15);

elsif(MEMORY_512M = '1' and WINDOW_NO = '1') then

RowChipPtr(14 downto 0) <= '0' & AD_R1(28 downto 15);

else -- when MEMORY_256M = '1' and WINDOW_NO = '1'

RowChipPtr(14 downto 0) <= "00" & AD_R1(27 downto 15);

end if;

elsif(ReadFIFOTailPtr_SDRAMPtr) then -- 4

if(MEMORY_2G = '0') then

RowChipPtr(14 downto 0) <= ReadFIFOTailPtr(29 downto 15);

else

RowChipPtr(14 downto 0) <= ReadFIFOTailPtr(30 downto 16);

end if;

elsif(MSDRAMPtr_SDRAMPtr) then -- 5

if(MEMORY_2G = '0') then

RowChipPtr(14 downto 0) <= MSDRAMPtr(29 downto 15);

else

RowChipPtr(14 downto 0) <= MSDRAMPtr(30 downto 16);

end if;

elsif(ModeValue_RowChipPtr) then -- 6

if(MEMORY_256M = '1') then

RowChipPtr(14 downto 0) <= "000" & X"027";

elsif(MEMORY_512M = '1') then

RowChipPtr(14 downto 0) <= "00" & X"027" & '0';

else -- MEMORY_1G_2G

RowChipPtr(14 downto 0) <= '0' & X"027" & "00";

end if;

elsif(RowChipPtrEnable) then -- 7

RowChipPtr <= RowChipPtr + '1';

end if;

end if;

end process;

For version of 'if..elsif..end' statement

Minimum period is 14.904ns.

Design Summary:

Number of errors: 0

Number of warnings: 77

Logic Utilization:

Number of Slice Flip Flops: 2,424 out of 10,240 23%

Number of 4 input LUTs: 5,346 out of 10,240 52%

Logic Distribution:

Number of occupied Slices: 3,432 out of 5,120 67%

Number of Slices containing only related logic: 3,432 out of

3,432 100%

Number of Slices containing unrelated logic: 0 out of

3,432 0%

*See NOTES below for an explanation of the effects of

unrelated logic

Total Number 4 input LUTs: 5,688 out of 10,240 55%

Number used as logic: 5,346

Number used as a route-thru: 108

Number used as 16x1 RAMs: 1

Number used as Shift registers: 233

Number of bonded IOBs: 272 out of 324 83%

IOB Flip Flops: 286

Number of Tbufs: 352 out of 2,560 13%

Number of GCLKs: 3 out of 16 18%

For manuaaly optimized version

Minimum period is 14.687ns.

Design Summary:

Number of errors: 0

Number of warnings: 77

Logic Utilization:

Number of Slice Flip Flops: 2,425 out of 10,240 23%

Number of 4 input LUTs: 5,252 out of 10,240 51%

Logic Distribution:

Number of occupied Slices: 3,369 out of 5,120 65%

Number of Slices containing only related logic: 3,369 out of

3,369 100%

Number of Slices containing unrelated logic: 0 out of

3,369 0%

*See NOTES below for an explanation of the effects of

unrelated logic

Total Number 4 input LUTs: 5,581 out of 10,240 54%

Number used as logic: 5,252

Number used as a route-thru: 95

Number used as 16x1 RAMs: 1

Number used as Shift registers: 233

Number of bonded IOBs: 272 out of 324 83%

IOB Flip Flops: 286

Number of Tbufs: 352 out of 2,560 13%

Number of GCLKs: 3 out of 16 18%