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vector assignment in VHDL

 
 
Vadim Rusu
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      06-18-2004
Hi,

I am trying to have a std_logic_vector which I want to define based on a
variable. In other words, say I have the vector V(31 downto 0) and I
only use RAM_SIZE bits. The rest of the vector I want to assign to 0. Is
there any way I can do this? So instead of having

V(31-RAM_SIZE downto 0)= "0000000000000"

I want something more elegant, like:

V(31-RAM_SIZE downto 0) = (32-RAM_SIZE) "0"

Is this doable in vhdl?


Thanks,
Vadim
 
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Symon
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      06-18-2004
V(31-RAM_SIZE downto 0) <= (others => '0');
Syms.


 
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ZOLVEZ ZOLVEZ is offline
Junior Member
Join Date: Oct 2007
Posts: 8
 
      10-02-2007
hi

I wonder if you could help me please

I want to discard bits of a signal of type std_logic_vector
for instance:

port (a, b : in std_logic_vector (15 downto 0)
c : out std_logic_vector (7 downto 0));

architecture a of xxx is
signal tmp : std_logic_vector (15 downto 0);

begin
tmp<= a and b;
c<= tmp (11 downto 4); ---that's I want to do

It means I want to use only some bits of tmp. I'm using ISE of XILINX
and it doesn't sinthesize it so I'd like to know another way please

thanks
 
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ZOLVEZ ZOLVEZ is offline
Junior Member
Join Date: Oct 2007
Posts: 8
 
      10-02-2007
hi

I wonder if you could help me please

I want to discard bits of a signal of type std_logic_vector
for instance:

port (a, b : in std_logic_vector (15 downto 0)
c : out std_logic_vector (7 downto 0));

architecture a of xxx is
signal tmp : std_logic_vector (15 downto 0);

begin
tmp<= a and b;
c<= tmp (11 downto 4); ---that's I want to do

It means I want to use only some bits of tmp. I'm using ISE of XILINX
and it doesn't sinthesize it so I'd like to know another way please. Any suggestion to ZOLVEZ@hotm... thanks a lot before hand

thanks
 
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