«

Hi,

is it possible to simulate under Modelsim (OEM Altera 5.7e)
a testbench (without any timing information) which includes
a module with an SDF file? (The SDF file is attached under
---> Simulate --> SDF ----> Add SDF file FILENAME_vhd.sdo + Apply to
region u1 (instantiation name of the module in the testbench)


I would appreciate your help because Altera seems not to be able
to respond to that question.

Thank you.

> is it possible to simulate under Modelsim (OEM Altera 5.7e)
> a testbench (without any timing information) which includes
> a module with an SDF file?

Of course it is.


> (The SDF file is attached under ---> Simulate --> SDF ----> Add SDF file
> FILENAME_vhd.sdo + Apply to region u1 (instantiation name of the module
> in the testbench)

What goes wrong there, then?
You don't provide much information about the problem.
--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

Hi,

it is a general question, I ask myself if that is possible.

I mean the stimuli created in the testbench are created in processes with the
clock with which my design under test is fed.

Of course when not defining it there is no clock-to-output time
for the registers that is there would be some violations concerning
tCO, tSU ... for the stimuli

But do these violatons make such a simulation impossible?

My problem is that I get an error message when trying to start
backannotated simulation:
"Fatal : SDR files require Altera primitive library."

It seems as if Altera is not able to give an answer to that problem.

In the workspace of Modelsim (OEM version for Altera 5.7e) there is
shown a Altera specific primitive library "cyclone".
Its type is shown to be LIBRARY and the Path is shown to be
$MODEL_TECH/../altera/vhdl/cyclone
So it is the installation path of Modelsim.
But how do I map it to my working directory?
(My library work has the path "modelsim_work".

How can I solve that problem?

Kind regards




Nicolas Matringe <> wrote in message news:<>...
> > is it possible to simulate under Modelsim (OEM Altera 5.7e)
> > a testbench (without any timing information) which includes
> > a module with an SDF file?
>
> Of course it is.
>
>
> > (The SDF file is attached under ---> Simulate --> SDF ----> Add SDF file
> > FILENAME_vhd.sdo + Apply to region u1 (instantiation name of the module
> > in the testbench)
>
> What goes wrong there, then?
> You don't provide much information about the problem.

(ALuPin) wrote in message news:<. com>...

> Of course when not defining it there is no clock-to-output time
> for the registers that is there would be some violations concerning
> tCO, tSU ... for the stimuli
>
> But do these violations make such a simulation impossible?

Read this:

http://www.itc-electronics.com/CD/al...5/an/an238.pdf

Infer, don't instance, shifters, counters, ram etc.
Do functional sims and static timing.
You don't have to worry about tCO and tSU
for synchronous designs. Just fmax.
And you don't have to worry about compiling
vendor libraries.

-- Mike Treseler