I see a lot changes in the design and verification effort, and VHDL is only a
small aspect of the picture. Assertion-Based Verification (ABV) with languages
like PSL or SystemVerilog are gaining popularity. PSL supports Verilog and
VHDL and is used to specify requirements at the top level and interface levels,
along with design properties for the RTL level. PSL follows many of the rules
of the native language that it supports. Many engineers feel that VHDL is
restrictive for verification because it lacks the ability to traverse levels of
design hierarchy, and to read output ports, both needed for PSL or for regular
testbench designs. Those engineers "hate" those aspects of the VHDL, and
prefer Verilog.
VHDL200x provides many improvements in VHDL, including traversing the
hierarchy, reading output ports, interfaces, and support of PSL. For the
record, SystemVerilog 3.1a LRM is out (
http://www.accellera.org/), and many
tool vendors are beginning to support it -- a very important factor.
SystemVerilog provides several features in the field of design and
verification, including an agressive assertion language, though comparable in
many respects to PSL.
<Surely I am becoming a VHDL nut...>
My suggestion before becoming a VHDL nut is to look at the whole design
environment, and languages that support this environment (now and in the
future). You may change your views on what "nut" to like.

Ben
-----------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.vhdlcohen.com/
Author of following textbooks:
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------