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How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?

 
 
Chao
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      06-10-2004
Hi, there

I am dealing with the back-annotated SDF timing simulation. The
timing_vhdl file is generated by the Xilinx ISE tool and I applied it
to the Modelsim simulator. But how can I obtain my original
input/output signal? With older tools, I can identify, for instance,
...._D is the input of Data FF, ..._Q is the output of Data FF. But now
I cannot trace these signals any more. It is dissappeard. How can I
work around this problem? Which abbreviate is short for input or
output of data flip-flop? I would appreciate any idea and suggestions.
Thanks.

Chao.
 
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Mike Treseler
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      06-11-2004
http://www.velocityreviews.com/forums/(E-Mail Removed) (Chao) wrote in message news:<(E-Mail Removed). com>...

> I am dealing with the back-annotated SDF timing simulation. The
> timing_vhdl file is generated by the Xilinx ISE tool and I applied it
> to the Modelsim simulator. But how can I obtain my original
> input/output signal?


Maybe you are using a component instance,
and need a configuration.
Here's an example:
____________________________________________
-- vital entity by place+route
-- vho = /usr0/tres/vhdl/xszero/synth/work
configuration vital of test_xszero is
for sim
for dut:socket
use entity vho.xszero(\ep1k50fc256-1\);
end for;
end for;
end configuration vital;
______________________________________________

Or maybe you haven't written a vhdl testbench yet.
It is signals from the testbench architecture.
that drive your design instance.

-- Mike Treseler
 
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ALuPin
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      06-14-2004
When simulating .sdf in Modelsim, I can see the registered signal names
of my VHDL description apart from many other gate level names.

Should I not be able to see the "original" registered names?

Thank you.

Kind regards
 
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Chao
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      06-14-2004
At first thanks for Mike's answer. But my exact question was how to
extract so many many internal signals which are listed during the
timing simulation. For example, _inbuf, _ibuf, _gst, etc. How can I
know which signal represents my original input signal or output
signal?

(E-Mail Removed) (Mike Treseler) wrote in message news:<(E-Mail Removed). com>...
> (E-Mail Removed) (Chao) wrote in message news:<(E-Mail Removed). com>...
>
> > I am dealing with the back-annotated SDF timing simulation. The
> > timing_vhdl file is generated by the Xilinx ISE tool and I applied it
> > to the Modelsim simulator. But how can I obtain my original
> > input/output signal?

>
> Maybe you are using a component instance,
> and need a configuration.
> Here's an example:
> ____________________________________________
> -- vital entity by place+route
> -- vho = /usr0/tres/vhdl/xszero/synth/work
> configuration vital of test_xszero is
> for sim
> for dut:socket
> use entity vho.xszero(\ep1k50fc256-1\);
> end for;
> end for;
> end configuration vital;
> ______________________________________________
>
> Or maybe you haven't written a vhdl testbench yet.
> It is signals from the testbench architecture.
> that drive your design instance.
>
> -- Mike Treseler

 
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Mike Treseler
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      06-14-2004
Chao wrote:
> At first thanks for Mike's answer. But my exact question was how to
> extract so many many internal signals which are listed during the
> timing simulation. For example, _inbuf, _ibuf, _gst, etc. How can I
> know which signal represents my original input signal or output
> signal?


The job of synthesis is to create a netlist of primitives
(like dffe, inbuf etc. ) that sims the same as your code.
You can view the netlist on tools like leonardo.
I don't know of any way to relate primitives to your
source code.

Normally synthesis "just works".
When it doesn't consider the following.

1. Double check the static timing report and synthesis warnings.
2. Eliminate asynchronous processes and multiple clocks.
3. Double check all inputs for synchronization.
4. Break the design into pieces zoom in on the problem.

Good luck,

-- Mike Treseler
 
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