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I use Cadence simvision for my simulations but I noticed that i could
not reset the simulation once it started when using systemc blocs in
my configuration.

My testbench uses vhdl but it uses some components writen in c++ .
Is there a solution , do you know if it's possible to reset simulation
with this simulator with systemc files ?

my problem is that I'd like to carry out a batch of simulation (>
1000) but it takes a long time since I have to launch simvision for
each simulation.

tks,
Nicolas

<> wrote in message
news: om...
> I use Cadence simvision for my simulations but I noticed that i
could
> not reset the simulation once it started when using systemc blocs in
> my configuration.
>
> My testbench uses vhdl but it uses some components writen in c++ .
> Is there a solution , do you know if it's possible to reset
simulation
> with this simulator with systemc files ?
>
> my problem is that I'd like to carry out a batch of simulation (>
> 1000) but it takes a long time since I have to launch simvision for
> each simulation.
>

I found that "Reinvoke Simulation" works with SystemC, but Reset
doesn't.
However I think that Reinvoke Simulation is possibly too slow for
your application. Isn't there a way of reinvoking simulation, but
attaching
it to an existing instance of Simvision?

Could you write a simulation that doesn't use waveforms and write a
self-checking
testbench instead?

regards

Alan


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