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Problems with DPLLing

 
 
JohnP
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Posts: n/a
 
      06-09-2004
The VCXO is a voltage controlled Xtal - many people supply 'em including CTS
Reeves,
CMAC, Frequency Controls, Ecmelectronics etc

Note that VCXOs come in 2 type, fast make and regular. You want fast make
for prototyping (as you are in a hurry) and regular for manufacture. If your
PCB
is crowded choose both types with the same footprint so you can swop out the
fast make for the regular without having to mount both devices.

The phase detector VDHL (to get back OT ) is

entity PLL_Mixer is
port (
output: buffer STD_LOGIC;
clk_in_1: in STD_LOGIC;
clk_in_2: in STD_LOGIC;
reset: in STD_LOGIC
);
end PLL_Mixer;

architecture PLL_Mixer_arch of PLL_Mixer is
signal clear: std_logic;
signal Q2: std_logic;
begin

D_Type1: process (reset, clk_in_1, clear)
begin
if reset ='0' then
output <= '0';
elsif clear ='1' then output <= '0';
elsif (clk_in_1 'event and clk_in_1 ='1' ) then
output <= '1';
end if;
end process pll_mixer1;

D_Type2: process (reset, clk_in_2, clear, output)
begin
if reset ='0' then
Q2 <= '0';
elsif clear ='1' then
Q2 <= '0';
elsif (clk_in_2 'event and clk_in_2 ='1' ) then
Q2 <= output;
end if;
end process pll_mixer2;
clear <= output AND Q2;
end pll_mixer_arch;

The frequency of "output" should be a few kilohertz so you likely will
have to divide down inputs clk_in_1 and clk_in_2, depending on what these
are. "output" goes to the OpAmp LP filter which drives the VCXO - Voila !

Mail me if you want a circuit diag.

Newbie


"MNQ" <(E-Mail Removed)> wrote in message
news:ca3mbk$gg5$(E-Mail Removed)...
> Hi Newbie
> Do you have any circuits diagrams or some thing that I can use to build a
> VCXO I hav'nt done this in a while?
>
> thanks
>
> Naveed
> "JohnP" <(E-Mail Removed)> wrote in message
> news:40c4c47a$(E-Mail Removed)...
> > Hi Naveen
> >
> > What you are doing is not a PLL. But a PLL is the traditional way to

> sync.
> > local and remote clocks. IF you can add an external OpAmp & VCXO to

your
> > logic device then the VHDL for the Phase Detector is simple.
> >
> > Newbie
> >
> > "MNQ" <(E-Mail Removed)> wrote in message
> > news:c9mr9a$5tv$(E-Mail Removed)...
> > > Hi All
> > >
> > > I'm trying to write some code to synchronise my local clock with some
> > > incoming data. At the moment when the receiver sees a specific bit

> > pattern,
> > > it makes pattern go to logic 1 for one clock period. This resets my

> clock
> > > and adds a small delay to my 2MHz clock. If I use this method I

> > effectively
> > > loose a clock cycle which I cannot afford. I want to reset my clock

on
> > the
> > > rising edge of pattern, but when I use the code
> > >
> > > If pattern='1' and pattern'event then clock_divide<="00010" ;
> > >
> > > I get a bad synchronous error when I synthesize
> > >
> > > Am I correct in thinking that this is a digital phase locked loop?
> > >
> > > Can anyone suggest a way of doing this as I have no idea at the moment

> and
> > > time is slipping by.
> > >
> > > Thanks for any help
> > >
> > >
> > > clk = 65.536MHz
> > > clock_2MHz should be 2.048MHz
> > > CPLD is XC2C384
> > >
> > > clock_divider : PROCESS (clk, pattern)
> > > BEGIN
> > > IF pattern='1' THEN clock_divide <= "00010";
> > > ELSIF clk='1' AND clk'event THEN
> > > clock_divide <= clock_divide - 1;
> > > END IF;
> > > END PROCESS clock_divider;
> > >
> > > clock_2MHz <= clock_divide(4);
> > >
> > >
> > > --
> > > Mr Naveed Qayyum
> > >
> > > www.mnq.org.uk
> > >
> > >

> >
> >

>
>



 
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johnp
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      06-09-2004
And THIS is my corect mail addy - - - sorry for that.
"JohnP" <(E-Mail Removed)> wrote in message news:40c6b9e4


 
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