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VHDL - state-machine

 
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Old 06-03-2004, 07:37 AM   #1
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Hi,
I've got 3 components: a data ackquirer, a CRC generator and a Manchester
Encoder. I was wondering if it was possible to use these in a state machine?
Because then I could set the enable/load_frame/shift/etc signal in each
state... Any point in the right direction is highly appreciated.

Cheers, Runar




Runar Gjelsvik
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