Drivers in subprograms

Hi experts,

I am looking at the code example on Fig. 7.2.6-2 in VHDL Coding Styles and
Methodologies by Ben Cohen and struggling to understand what the Data_s is
supposed to look like? Are those waits in the procedure supposed to do
something? I have simulated it and they seem to be doing nothing... The
data changes only on clock...

Thanks,
/Mikhail

MM

"MM" <> wrote in message news:<>...
> Hi experts,
>
> I am looking at the code example on Fig. 7.2.6-2 in VHDL Coding Styles and
> Methodologies by Ben Cohen and struggling to understand what the Data_s is
> supposed to look like? Are those waits in the procedure supposed to do
> something? I have simulated it and they seem to be doing nothing... The
> data changes only on clock...
>
> Thanks,
> /Mikhail

This model was for demo only and not for synthesis. It demonstrates
that from a process, a call to a procedure, with the formal designator
class SIGNAL, an mode inout is the same as having the procedure
inline. All the drivers belong to the process. Those waits were to
just generate a set of simple waiforms, triggered after the rising
edge of the clock.
Ben Cohen
-----------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.vhdlcohen.com/
Author of following textbooks:
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition,
2004 isbn 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
------------------------------------------------------------------------------

ben cohen

Hello Ben,

> This model was for demo only and not for synthesis. It demonstrates
> that from a process, a call to a procedure, with the formal designator
> class SIGNAL, an mode inout is the same as having the procedure
> inline. All the drivers belong to the process. Those waits were to
> just generate a set of simple waiforms, triggered after the rising
> edge of the clock.

I understand that it was not intended for synthesis... I am running it under
a VHDL simulator (Active HDL 6.2). The problem is that "the simple waveform"
is not being generated as if there were no waits in the procedure... Is that
a problem with my simulator?

Thanks,
/Mikhail

MM

>I understand that it was not intended for synthesis... I am running it under
>a VHDL simulator (Active HDL 6.2). The problem is that "the simple waveform"
>is not being generated as if there were no waits in the procedure... Is that
>a problem with my simulator?
>
>Thanks,
>/Mikhail

Works for me in ModelSim. Below is a list of the results.
ns /driver/clk_s
delta /driver/data_s
0 +0 0 10101011
50000 +0 1 10101011
50000 +1 1 01010100
50100 +1 1 10101011
50300 +1 1 01010100
100000 +0 0 01010100
150000 +0 1 01010100
150000 +1 1 10101011
150100 +1 1 01010100
150300 +1 1 10101011
200000 +0 0 10101011
Perhaps you missed the waveforms at the rising edge of the clock because of the

scalings (large period for clock, fast transitions near clock edge).
Ben Cohen
www.vhdlcohen.com

VhdlCohen

> Perhaps you missed the waveforms at the rising edge of the clock because
of the
> scalings (large period for clock, fast transitions near clock edge).

Yes! You are right! Stupid me...

Thanks,
/Mikhail

MM