Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Simulating VHDL design with ModelSim

Reply
Thread Tools

Simulating VHDL design with ModelSim

 
 
Modukuri
Guest
Posts: n/a
 
      05-27-2004
Hi:

I'm using ModelSim SE-64 PLUS 5.5f to simulate my VHDL
designs.Recently,I tried simulating a design with input data files of
size (85kb).I left the simulation to run overnight,but I still haven't
got any results.I checked the status of "vsim"
by typing in the following at the command prompt.
ps -ef | grep vsim

It showed that vsim is still running and the CPU usage is only 25%.
I'm not sure if this is due to the file size???

Please help!!

Thanks,
Modukuri
 
Reply With Quote
 
 
 
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      05-27-2004
Modukuri wrote:

> I'm using ModelSim SE-64 PLUS 5.5f to simulate my VHDL
> designs.Recently,I tried simulating a design with input data files of
> size (85kb).I left the simulation to run overnight,but I still haven't
> got any results.


Do you simulate behavioral descriptions or synthesitzed netlists (with sdf)?

What happens, if you stop the simulation (an run it again, starting from
the stop position)?


Check your source code for infinite loops:

process(enable,data)
begin
if (enable='1') then -- latch
data<=data+1; -- infinite loop - DON'T DO THIS
end if;
end process;


Ralf

 
Reply With Quote
 
 
 
 
Modukuri
Guest
Posts: n/a
 
      05-27-2004
I'm simulating behavioral descriptions (using vsim GUI).AS modelsim
window is not responding during the simulation,I'm unable to break the
simulation at any point except to kill the whole process.But that is
closing vsim completely.Is there any way to check,if the process is
actually updating the signals/ just executing the loops infinetely?
Below is part of my code.I tested my code in parts and it was working
fine until this process.I'm not sure, if the loops are causing the
problem??

process(clk,reset,sdata,cdata)
variable current_blk : data_array;
variable search_blk : data_array;
begin
if reset = '1' then
current_blk := data1;
search_blk := data1;
SAD_CMP <= SAD_ini;
elsif (clk'event and clk = '1') then
for m in 1 to 36 loop
for n in 1 to 44 loop
for i in ((m-1)*blksize) to ((blksize*m)-1) loop
for j in ((n-1)*blksize) to ((blksize*n)-1) loop
current_blk(i,j) := cdata(i,j);
cblk(i,j) <= current_blk(i,j);
for k in 0 to 3 loop
for l in 0 to 3 loop
for x in ((i-1)+pvec(k)) to ((i+pvec(k))) loop
for y in ((j-1)+pvec(l)) to ((j+pvec(l))) loop
if (x <= 143 and y <= 175) then
search_blk(x,y) := sdata(x,y);
sblk(x,y) <= search_blk(x,y);
for u in 0 to 143 loop
for v in 0 to 175 loop
if (sblk(u,v) >= cblk(u,v)) then
SAD_CMP(u,v) <= sblk(u,v) - cblk(u,v);
else
SAD_CMP(u,v) <= cblk(u,v) - sblk(u,v);
end if;
end loop;
end loop;
end if;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end if;

I would appreciate any help/advice.

Thanks a lot,
Modukuri

Ralf Hildebrandt <(E-Mail Removed)> wrote in message news:<(E-Mail Removed)>...
> Modukuri wrote:
>
> > I'm using ModelSim SE-64 PLUS 5.5f to simulate my VHDL
> > designs.Recently,I tried simulating a design with input data files of
> > size (85kb).I left the simulation to run overnight,but I still haven't
> > got any results.

>
> Do you simulate behavioral descriptions or synthesitzed netlists (with sdf)?
>
> What happens, if you stop the simulation (an run it again, starting from
> the stop position)?
>
>
> Check your source code for infinite loops:
>
> process(enable,data)
> begin
> if (enable='1') then -- latch
> data<=data+1; -- infinite loop - DON'T DO THIS
> end if;
> end process;
>
>
> Ralf

 
Reply With Quote
 
Mike Treseler
Guest
Posts: n/a
 
      05-28-2004
Modukuri wrote:
> I'm simulating behavioral descriptions (using vsim GUI).AS modelsim
> window is not responding during the simulation,I'm unable to break the
> simulation at any point except to kill the whole process.
>
> process(clk,reset,sdata,cdata)


Try process(clk,reset)
and make sure your sim clock waits when done.

--Mike Treseler

 
Reply With Quote
 
Marcus Harnisch
Guest
Posts: n/a
 
      05-28-2004
Ralf Hildebrandt <(E-Mail Removed)> writes:

> Check your source code for infinite loops:


Versions of ModelSim I work with, exit from zero-time loops after
5000(?) cycles by default.

Modukuri seems to be concerned whether the loop updates signals at
all. Why not do a `run x ns', where `x' is the time it takes to
simulate a reasonably low number of clock cycles.

With loops like that I wouldn't recommend single stepping but printing
time stamps and loop variables can give valuable information, too.

-- Marcus

--
Marcus Harnisch | Mint Technology, a division of LSI Logic
http://www.velocityreviews.com/forums/(E-Mail Removed) | 200 West Street, Waltham, MA 02431
Tel: +1-781-768-0772 | http://www.lsilogic.com
 
Reply With Quote
 
Tim Hubberstey
Guest
Posts: n/a
 
      05-29-2004
Modukuri wrote:
> I'm simulating behavioral descriptions (using vsim GUI).AS modelsim
> window is not responding during the simulation,I'm unable to break the
> simulation at any point except to kill the whole process.But that is
> closing vsim completely.Is there any way to check,if the process is
> actually updating the signals/ just executing the loops infinetely?
> Below is part of my code.I tested my code in parts and it was working
> fine until this process.I'm not sure, if the loops are causing the
> problem??


Have you REALLY considered what you are doing here? Because of the
loops, the simulator must execute several hundred million iterations FOR
EACH CLOCK CYCLE, depending on the size of 'blksize'.

Even on the fastest workstation available, this is likely to take many
seconds per simulated clock cycle. I wouldn't be surprised to find that
it is many minutes, or even hours, per clock.

I also wouldn't be surprised to find that you've run out of physical
memory and forced the machine to start swapping. If this happens, your
simulation times will skyrocket.

As for ModelSim not responding to break requests, the last time I used
SE (several years ago) there was an issue with it not recognizing breaks
unless at least one signal was waved or logged (add [wave|log]).
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 
Reply With Quote
 
Allan Herriman
Guest
Posts: n/a
 
      05-31-2004
On Fri, 28 May 2004 15:32:53 -0400, Marcus Harnisch
<(E-Mail Removed)> wrote:

>Ralf Hildebrandt <(E-Mail Removed)> writes:
>
>> Check your source code for infinite loops:

>
>Versions of ModelSim I work with, exit from zero-time loops after
>5000(?) cycles by default.


Ummm, no. Only if delta time advances.

Regards,
Allan.
 
Reply With Quote
 
Marcus Harnisch
Guest
Posts: n/a
 
      06-01-2004
Allan Herriman <(E-Mail Removed)> writes:

> On Fri, 28 May 2004 15:32:53 -0400, Marcus Harnisch
> <(E-Mail Removed)> wrote:
>
>>Versions of ModelSim I work with, exit from zero-time loops after
>>5000(?) cycles by default.

>
> Ummm, no. Only if delta time advances.


Yes. But in the code example I was following up on delta time does
advance.

--
Marcus Harnisch | Mint Technology, a division of LSI Logic
(E-Mail Removed) | 200 West Street, Waltham, MA 02431
Tel: +1-781-768-0772 | http://www.lsilogic.com
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
VHDL-AMS: Simulating a closed model in Mentor Graphics System Vision shai.lesh@gmx.com VHDL 0 02-26-2013 09:18 AM
VHDL Generics problem when simulating SDF with Scirocco Fazela VHDL 1 04-29-2006 05:07 PM
How to use Modelsim 6.od for simulating systemc Baskar VHDL 0 03-06-2006 06:02 PM
Problem simulating Xilinx CoreGenerator Cores with ModelSim SE 5.8C. Jeremy Webb VHDL 2 10-23-2004 01:56 AM
VHDL design and ModelSim Vilvox VHDL 2 09-01-2003 06:23 PM



Advertisments