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i have implemented this vhdl code for divide the clock
p1 : process (clk_chip)
variable compteur : integer range 0 to 11;
begin
if (clk_chip'event )then
if reset='1' then
compteur := 1;
else if compteur >= 11 then
compteur := 1;
else
compteur := compteur + 1;
end if;
end if;
if compteur >= 6 then
clock_bit <= '0';
else
clock_bit <= '1';
end if;
end if;
end process p1;

but the counter not count the two edge !!

have you any idea ?

Patrick wrote:
> i have implemented this vhdl code for divide the clock
> p1 : process (clk_chip)
> variable compteur : integer range 0 to 11;
> begin
> if (clk_chip'event )then
> if reset='1' then
> compteur := 1;
> else if compteur >= 11 then
> compteur := 1;
> else
> compteur := compteur + 1;
> end if;
> end if;
> if compteur >= 6 then
> clock_bit <= '0';
> else
> clock_bit <= '1';
> end if;
> end if;
> end process p1;
>
> but the counter not count the two edge !!
>
> have you any idea ?

Some VHDL rules:

- do not use variable, but use signal
- if possible use asynchronous reset
- if possible do not use >= but only = , you will save in your clock
frequency

Laurent
www.amontec.com
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I have modified the process like this

p1 : process (clk_chip,reset)
variable compteur : integer range 0 to 11;
begin
if reset = '1' then
compteur := 1;
else if (clk_chip'event)then
if compteur = 11 then
compteur := 1;
else
compteur := compteur + 1;
end if;
if compteur >= 6 then
clk_bit <= '0';
else
clk_bit <= '1';
end if;
end if;
end if;
end process p1;


but when i synthesis this one on a stratix fpga, the counter count
only the rising edge and not the two rising and falling edge (use of
clk_chip'event ONLY) with Quartus II 4.0

seems to be that the flipflops could react only at rising or at falling
edge, not at both

take two processes, each responsible for a clock edge typ.
j

the synthesis software should have given you a warning ?


> I have modified the process like this
>
> p1 : process (clk_chip,reset)
> variable compteur : integer range 0 to 11;
> begin
> if reset = '1' then
> compteur := 1;
> else if (clk_chip'event)then
> if compteur = 11 then
> compteur := 1;
> else
> compteur := compteur + 1;
> end if;
> if compteur >= 6 then
> clk_bit <= '0';
> else
> clk_bit <= '1';
> end if;
> end if;
> end if;
> end process p1;
>
>
> but when i synthesis this one on a stratix fpga, the counter count
> only the rising edge and not the two rising and falling edge (use of
> clk_chip'event ONLY) with Quartus II 4.0

Patrick wrote:
> I have modified the process like this
>
> p1 : process (clk_chip,reset)
> variable compteur : integer range 0 to 11;
> begin
> if reset = '1' then
> compteur := 1;
> else if (clk_chip'event)then
> if compteur = 11 then
> compteur := 1;
> else
> compteur := compteur + 1;
> end if;
> if compteur >= 6 then
> clk_bit <= '0';
> else
> clk_bit <= '1';
> end if;
> end if;
> end if;
> end process p1;
>
>
> but when i synthesis this one on a stratix fpga, the counter count
> only the rising edge and not the two rising and falling edge (use of
> clk_chip'event ONLY) with Quartus II 4.0

Dual-edge-behavior is not supported by VHDL at the moment. If you would
have mentioned, that your code has to be synthesized, you would have got
an answer to your 1st posting.

I am only in wonder, why your synthesis tool did not exit with an error.


Ralf

Ralf Hildebrandt wrote:
> Patrick wrote:
>
>> I have modified the process like this
>>
>> p1 : process (clk_chip,reset)
>> variable compteur : integer range 0 to 11;
>> begin
>> if reset = '1' then
>> compteur := 1;
>> else if (clk_chip'event)then
>> if compteur = 11 then
>> compteur := 1;
>> else
>> compteur := compteur + 1;
>> end if;
>> if compteur >= 6 then
>> clk_bit <= '0';
>> else clk_bit <= '1';
>> end if;
>> end if;
>> end if;
>> end process p1;
>>
>>
>> but when i synthesis this one on a stratix fpga, the counter count
>> only the rising edge and not the two rising and falling edge (use of
>> clk_chip'event ONLY) with Quartus II 4.0
>
>
> Dual-edge-behavior is not supported by VHDL at the moment. If you would
> have mentioned, that your code has to be synthesized, you would have got
> an answer to your 1st posting.
>
> I am only in wonder, why your synthesis tool did not exit with an error.
>
>
> Ralf
>

It's WRONG !

This is depending on the architecture target only, but this is not
depending on the VHDL language.

For many projects we used the dual-edge VHDL description and it works
fine for simulation, for synthesis and for Place and Route.

Just try to place and route the code to an Xilinx CoolRunner-II and your
count will run on both edges.

It just CANNOT work for stratix FPGA, because the stratix achitechture
does not support the dual-edge !

Laurent Gauch
www.amontec.com

"Amontec, Larry" <> wrote in message
news:...
> Patrick wrote:
> > i have implemented this vhdl code for divide the clock
> > p1 : process (clk_chip)
> > variable compteur : integer range 0 to 11;
> > begin
> > if (clk_chip'event )then
> > if reset='1' then
> > compteur := 1;
> > else if compteur >= 11 then
> > compteur := 1;
> > else
> > compteur := compteur + 1;
> > end if;
> > end if;
> > if compteur >= 6 then
> > clock_bit <= '0';
> > else
> > clock_bit <= '1';
> > end if;
> > end if;
> > end process p1;
> >
> > but the counter not count the two edge !!
> >
> > have you any idea ?
>
> Some VHDL rules:
Huh? Where did you get these "rules"?
>
> - do not use variable, but use signal
The use of variables should be fine in this case, if your synthesis
tools can handle it.
> - if possible use asynchronous reset
In general, asynchrounous resets are problematic. I would recommend
synchronous resets wherever possible.
> - if possible do not use >= but only = , you will save in your clock
compteur is defined as having a range of 0 to 11 so the >= comparison is
unnecessary because the variable can never be > 11. Also, you defined
the range as 0 to 11 but in your code compteur never has a value of 0,
so the range should probably be 1 to 11.
> frequency
>
> Laurent
> www.amontec.com
> ------------ And now a word from our sponsor ------------------
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> fast, efficient and reliable. For home servers or carrier class
> installations with millions of users it will allow you to grow!
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