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VHDL - resolved/unresolved signal?!

 
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Old 05-16-2004, 02:10 PM   #1
Default resolved/unresolved signal?!


I have made my own type and defined a signal of my tipe:

type my_type is (zero, first, sec, third, fourth);
SIGNAL floor : my_type;

and when I Save and check..., I get the message that says:
floor is multiply driven (or smthn like that).

What does it mean?

I tried writing
SIGNAL floor : resolved my_type;
but than says "can't find resolver smthn...".

What should I do? Please help!

Thank you.





jozo
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Old 05-16-2004, 03:47 PM   #2
Ralf Hildebrandt
 
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Default Re: resolved/unresolved signal?!
jozo wrote:
> I have made my own type and defined a signal of my tipe:
>
> type my_type is (zero, first, sec, third, fourth);
> SIGNAL floor : my_type;
>
> and when I Save and check..., I get the message that says:
> floor is multiply driven (or smthn like that).


Your write to signal floor from multiplie processes - e.g.:

process(...)
begin
if rising_edge(...) then
floor<= ....
end if;
end process;

floor<= ....

process(....)
begin
if (...) then
floor<=...
end if;
end process;


Don't do this (except you want to design a tri-state multiplexer). Write
to a signal only from one process.


Ralf



Ralf Hildebrandt
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