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VHDL - compare unsigned

 
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Old 05-14-2004, 03:46 PM   #1
Default compare unsigned


Hello,

I have a VHDL-beginner question:

How do I compare an unsigned signal to a value, when I don´t know the
width of this unsigned(the width depends on a parameter)?

At the moment I do it like this:

if to_integer(my_unsigned_value) = 1 then ...

But I have know idea, what the synthesis makes out of this construct (I
guess a comparator with 32 bits).

Can anyone help?

Thanks,
Matthias


Matthias Alles
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Old 05-14-2004, 04:14 PM   #2
Mike Treseler
 
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Default Re: compare unsigned
Matthias Alles wrote:

> At the moment I do it like this:
>
> if to_integer(my_unsigned_value) = 1 then ...


if my_unsigned_value = 1 then ...

will also work for numeric_std.

> But I have know idea, what the synthesis makes out of this construct (I
> guess a comparator with 32 bits).


Synthesis will use the correct width.
Try it yourself and see.

-- Mike Treseler


Mike Treseler
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